Patent Assignment
Reel/Frame 056702/0712
Merger and Change of Name
Recorded: 2021-06-29
Pages: 7
Assignors
MENTOR GRAPHICS CORPORATION
Executed: 2020-12-30
SIEMENS INDUSTRY SOFTWARE INC.
Executed: 2020-12-30
Assignee
SIEMENS INDUSTRY SOFTWARE INC.
5800 GRANITE PARKWAY, SUITE 600, PLANO, TEXAS, 75024
Covered Properties
(92)
Method for Synthesizing Linear Finite State Machines
Interactive Loop Configuration in a Behavioral Synthesis Tool
Integrating Multiple Electronic Design Applications
Full-Speed Bist Controller for Testing Embedded Synchronous Memories
Asymmetric Data Path Media Access Controller
Fault Diagnosis of Compressed Test Responses Having One or More Unknown States
Synchronization Point Across Different Memory Bist Controllers
Hierarchical Presentation Techniques for a Design Tool
Hierarchical Presentation Techniques for a Design Tool
Test Pattern Compression for an Integrated Circuit Test Environment
Secure Exchange of Information in Electronic Design Automation
Compactor Independent Fault Diagnosis
Distributed Autorouting of Conductive Paths
Method for Synthesizing Linear Finite State Machines
Dynamic Verification Traversal Strategies
Compressing Test Responses Using a Compactor
Dram Architecture
Integrated Opc Verification Tool
Interactive Loop Configuration in a Behavioral Synthesis Tool
Method and Apparatus for Selectively Compacting Test Responses
Decompressor/Prpg for Applying Pseudo-Random and Deterministic Test Patterns
Test Pattern Compression for an Integrated Circuit Test Environment
Fault Diagnosis of Compressed Test Responses
Phase Shifter with Reduced Linear Dependency
Contrast-Based Resolution Enhancement for Photolithographic Processing
Phase Shifter with Reduced Linear Dependency
Parallel Electronic Design Automation: Shared Simultaneous Editing
Secure Exchange of Information in Electronic Design Automation
Metastability Effects Simulation for a Circuit Description
Compactor Independent Direct Diagnosis of Test Hardware
Low Power Decompression of Test Cubes
Method and Apparatus for Selectively Compacting Test Responses
Sum of Coherent Systems (Socs) Approximation Based on Object Information
Hierarchical Presentation Techniques for a Design Tool
Fragmentation Point and Simulation Site Adjustment for Resolution Enhancement Techniques
Continuous Application and Decompression of Test Patterns and Selective Compaction of Test Responses
Simultaneous Multi-Layer Fill Generation
Decompressors for Low Power Decompression of Test Patterns
Design-Rule-Check Waiver
Conversion of Circuit Description to an Abstract Model of the Circuit
Conversion of Circuit Description to an Abstract Model of the Circuit
Determining Mutual Inductance Between Intentional Inductors
High-Frequency Vlsi Interconnect and Intentional Inductor Impedance Extraction in the Presence of a Multi-Layer Conductive Substrate
Power State Transition Verification For Electronic Design
Model-Based Fill
Layout Content Analysis for Source Mask Optimization Acceleration
Sub-Resolution Assist Feature Repair
Layout Design Defect Repair Based On Inverse Lithography And Traditional Optical Proximity Correction
Layout Design Defect Repair Using Inverse Lithography
Measure of Analysis Performed in Property Checking
Input Space Reduction for Verification Test Set Generation
Metastability Effects Simulation for a Circuit Description
Fault-Driven Scan Chain Configuration For Test-Per-Clock
Scan Chain Stitching for Test-Per-Clock
Hierarchical Feature Extraction for Electrical Interaction Calculations
Analysis Optimizer
Density-Based Integrated Circuit Design Adjustment
Continuous Application and Decompression of Test Patterns and Selective Compaction of Test Responses
Mutual Inductance Extraction Using Dipole Approximations
Trace Routing Network
Fragmentation Point and Simulation Site Adjustment for Resolution Enhancement Techniques
Fault Support in an Emulation Environment
Random Access Memory for Use in an Emulation Environment
Circuit and Method for Measuring Delays between Edges of Signals of a Circuit
High-Frequency Vlsi Interconnect and Intentional Inductor Impedance Extraction in the Presence of a Multi-Layer Conductive Substrate
Selective Per-Cycle Masking of Scan Chains for System Level Test
Layout Content Analysis for Source Mask Optimization Acceleration
Third Party Component Debugging for Integrated Circuit Design
High-Frequency Vlsi Interconnect and Intentional Inductor Impedance Extraction in the Presence of a Multi-Layer Conductive Substrate
Generating Test Sets for Diagnosing Scan Chain Failures
System Design Management
Timing-Aware Test Generation and Fault Simulation
Continuous Application and Decompression of Test Patterns and Selective Compaction of Test Responses
Domain Bounding For Symmetric Multiprocessing Systems
Electrostatic Damage Protection Circuitry Verification
Measure of Analysis Performed in Property Checking
Resource Mapping in a Hardware Emulation Environment
Multi-Mode Multi-Corner Clocktree Synthesis
Source Optimization for Image Fidelity and Throughput
Test-Per-Clock Based on Dynamically-Partitioned Reconfigurable Scan Chains
Fragmentation Point and Simulation Site Adjustment for Resolution Enhancement Techniques
Selective Per-Cycle Masking of Scan Chains for System Level Test
Simultaneous Multi-Layer Fill Generation
Continuous Application and Decompression of Test Patterns and Selective Compaction of Test Responses
Fragmentation Point and Simulation Site Adjustment for Resolution Enhancement Techniques
Multi-Mode Multi-Corner Clocktree Synthesis
Patent:
10,146,897 →
Application:
15/669,827 →
Latency Test in Networking System-on-Chip Verification
Bandwidth Test In Networking System-On-Chip Verification
Formal Verification Using Microtransactions
Patent:
10,515,168 →
Application:
15/809,892 →
Data Streaming for Testing Identical Circuit Blocks
Patent:
10,473,721 →
Application:
15/925,655 →
Streaming Networks Efficiency Using Data Throttling
Patent:
10,775,436 →
Application:
15/925,657 →
Verification of Photonic Integrated Circuits
Related Assignments
(20)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Feb 17, 2004
From: RAJSKI, JANUSZ; TYSZER, JERZY; KASSAB, MARK; MUKHERJEE, NILANJAN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015009/0156 →
Assignment of Assignor's Interest
Aug 30, 2004
From: BURNETTE, DAVID GAINES; GUTBERLET, PETER PIUS
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015761/0945 →
Assignment of Assignor's Interest
Nov 8, 2004
From: PETUNIN, VLADIMIR V.
To: MENTOR GRAPHICS
Reel/Frame 015992/0426 →
Assignment of Assignor's Interest
Dec 3, 2004
From: CHENG, WU-TUNG; HILL, CHRISTOPHER JOHN; KEBICHI, OMAR
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015424/0134 →
Assignment of Assignor's Interest
Jan 14, 2005
From: TATE, MICHAEL
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 015598/0256 →
Assignment of Assignor's Interest
Nov 22, 2005
From: RAJSKI, JANUSZ; MRUGALSKI, GRZEGORZ; POGIEL, ARTUR; TYSZER, JERZY
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 016809/0189 →
Assignment of Assignor's Interest
Oct 25, 2006
From: RAJSKI, JANUSZ; TYSZER, JERZY; KASSAB, MARK; MUKHERJEE, NILANJAN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 018449/0443 →
Assignment of Assignor's Interest
Oct 25, 2006
From: KEBICHI, OMAR; CHENG, WU-TUNG; HILL, CHRISTOPHER JOHN; REUTER, PAUL J.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 018449/0567 →
Assignment of Assignor's Interest
Oct 11, 2007
From: PETUNIN, VLADIMIR V.; PFEIL, CHARLES L.; NATARAJAN, VENKAT; SMITH, EDWIN FRANKLIN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 019950/0156 →
Assignment of Assignor's Interest
Oct 11, 2007
From: STARKOV, ALEXANDER N.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 019950/0183 →
Assignment of Assignor's Interest
Feb 7, 2008
From: CHENG, WU-TUNG; HUANG, YU; TSAI, KUN-HAN; RAJSKI, JANUSZ
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 020486/0683 →
Assignment of Assignor's Interest
Mar 19, 2008
From: RAJSKI, JANUSZ; WANG, CHEN; MRUGALSKI, GRZEGORZ; TYSZER, JERZY
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 020674/0312 →
Assignment of Assignor's Interest
Jul 21, 2009
From: KADKADE, SUDHIR DATTARAM; LYONS, CLIFTON ALTON, JR
To: LIGHTHOUSE DESIGN AUTOMATION, INC.
Reel/Frame 022980/0612 →
Assignment of Assignor's Interest
Jul 22, 2009
From: LIGHTHOUSE DESIGN AUTOMATION, INC.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 022980/0956 →
Assignment of Assignor's Interest
Aug 6, 2009
From: GUTBERLET, PETER P; WATERS, SIMON J; BOWYER, BRYAN D
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 023064/0509 →
Assignment of Assignor's Interest
Oct 22, 2009
From: RAJSKI, JANUSZ; TYSZER, JERZY; KASSAB, MARK; MUKHERJEE, NILANJAN
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 023411/0228 →
Assignment of Assignor's Interest
Jun 28, 2010
From: FERGUSON, JOHN G.; PIKUS, FEDOR G.; SAKAJIRI, KYOHEI; GRODD, LAURENCE W.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 024599/0225 →
Assignment of Assignor's Interest
Dec 15, 2010
From: GUTBERLET, PETER P.; WATERS, SIMON J.; BOWYER, BRYAN D.
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 025506/0450 →
Change of Name
May 17, 2011
From: NOVELICS, LLC
To: NOVELICS CORPORATION
Reel/Frame 026293/0263 →
Assignment of Assignor's Interest
May 19, 2011
From: NOVELICS CORPORATION
To: MENTOR GRAPHICS CORPORATION
Reel/Frame 026306/0510 →