Continuous application and decompression of test patterns and selective compaction of test responses
View Patent ↗A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
1. A system, comprising:
a circuit comprising a decompressor, the decompressor comprising a linear feedback shift register (LFSR); and
automatic testing equipment located external to the circuit,
wherein the decompressor is configured to load compressed test pattern data from an output of the automatic testing equipment through an input logic gate of the LFSR, the input logic gate of the LFSR being configured to receive the compressed test pattern data and logically combine the compressed test pattern data with data stored within the LFSR concurrently as the decompressor outputs decompressed test pattern data.
2. The system of claim 1 , wherein the decompressor is configured to receive multiple compressed test pattern bits in parallel from multiple outputs of the automatic testing equipment through multiple input gates of the LFSR.
3. The system of claim 1 , wherein the decompressor further includes a phase shifter having inputs coupled to outputs of the LFSR, the phase shifter being configured such that test pattern bits output from the phase shifter are out of phase with one another.
4. The system of claim 1 , wherein the circuit further includes scan chains and wherein the decompressor further includes a phase shifter coupled between the LFSR and the scan chains, the phase shifter being configured such that test pattern bits output from the phase shifter are out of phase with one another.
5. The system of claim 4 , wherein the circuit further comprises an XOR tree coupled to two or more outputs of the scan chains.
6. The system of claim 4 , wherein the circuit further comprises a compactor coupled to outputs of the scan chains.
7. The system of claim 6 , wherein the compactor comprises an XOR tree.
8. The system of claim 1 , wherein the circuit further comprises scan chains configured to receive decompressed test pattern bits from the decompressor.
9. The system of claim 8 , wherein the circuit further comprises a compactor coupled to outputs of the scan chains.
10. The system of claim 9 , wherein the compactor comprises an XOR tree.
11. The system of claim 1 , wherein the input logic gate is an XOR gate.