Continuous application and decompression of test patterns and selective compaction of test responses
View Patent ↗A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
1. A system, comprising:
a circuit comprising a register and a decompressor, the decompressor comprising a linear feedback shift register (LFSR); and
automatic testing equipment located external to the circuit,
wherein the register is configured to load compressed test pattern data from an output of the automatic testing equipment and to output the compressed test pattern data to an input logic gate of the LFSR, the input logic gate of the LFSR being configured to receive the compressed test pattern data and logically combine the compressed test pattern data with data stored within the LFSR.
2. The system of claim 1 , wherein the register is configured to receive multiple bits of the compressed test pattern data in parallel from multiple outputs of the automatic testing equipment before the multiple bits of the compressed test pattern data are output to the input logic gate of the LFSR.
3. The system of claim 1 , wherein the decompressor further includes a phase shifter having inputs coupled to outputs of the LFSR, the phase shifter being configured such that test pattern bits output from the phase shifter are out of phase with one another.
4. The system of claim 1 , wherein the circuit further includes scan chains and wherein the decompressor further includes a phase shifter coupled between the LFSR and the scan chains, the phase shifter being configured such that test pattern bits output from the phase shifter are out of phase with one another.
5. The system of claim 1 , wherein the register is configured to receive the compressed test pattern data in parallel from multiple outputs of the automatic testing equipment and shift the compressed test pattern into the LFSR.
6. A method, comprising:
loading a register within a circuit with compressed test pattern bits;
transferring the compressed test pattern bits from the register to a decompressor comprising a linear feedback shift register (LFSR); and
decompressing the compressed test pattern bits with the decompressor, wherein the decompressing comprises logically combining the compressed test pattern bits with bits stored within the decompressor.
7. The method of claim 6 , wherein the decompressor further comprises a phase shifter.
8. The method of claim 6 , wherein the decompressing occurs in the decompressor as the compressed test pattern bits are transferred from the register to the decompressor.
9. The method of claim 6 , wherein the loading comprises loading the compressed test pattern bits into the register from external automatic testing equipment (ATE).
10. The method of claim 6 , further including loading scan chains with the decompressed test pattern bits.
11. The method of claim 6 , wherein the loading comprises loading the compressed test pattern bits into the register in parallel, and wherein the transferring includes serially shifting the compressed test pattern bits from the register into the decompressor.