Continuous application and decompression of test patterns and selective compaction of test responses
A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.
1. A circuit, comprising:
a parallel-in serial-out register; and
a decompressor comprising a phase shifter and a linear feedback shift register (LFSR), the LFSR being coupled between an output of the register and an input of the phase shifter,
the parallel-in serial-out register being configured to load compressed test pattern bits in parallel and apply the compressed test pattern bits serially to the LFSR of the decompressor, and
the decompressor being configured to decompress the compressed test pattern bits into decompressed test pattern bits.
2. The circuit of claim 1 , wherein the parallel-in-serial-out register is coupled to automatic testing equipment (ATE) located externally to the circuit.
3. The circuit of claim 1 , further including scan chains coupled to the phase shifter.
4. The circuit of claim 1 , wherein the phase shifter is formed from only XOR gates.
5. The circuit of claim 1 , wherein the parallel-in serial-out register is coupled to automatic testing equipment (ATE) located externally to the circuit, the parallel-in serial-out register being configured to load the compressed test pattern from the ATE and output the compressed test pattern to the LFSR.
6. The apparatus of claim 1 , wherein the parallel-in serial-out register is a shift register.
7. The apparatus of claim 1 , wherein the parallel-in serial-out register is configured to apply the compressed test pattern bits serially to an XOR gate of the LFSR that is interposed between two respective memory elements of the LFSR.
8. The apparatus of claim 1 , wherein the parallel-in serial-out register is clocked such that its contents are shifted out before a next set of compressed test pattern bits is applied to the parallel-in serial-out register.
9. The apparatus of claim 1 , wherein the parallel-in serial-out register is a first parallel-in serial-out register, the apparatus further comprising a second parallel-in serial-out register that is also configured to load respective compressed test pattern bits in parallel and apply the respective compressed test pattern bits serially to the LFSR of the decompressor.