Bandwidth test in networking System-on-Chip verification
Aspects of the disclosed technology relate to techniques of bandwidth test in networking system-on-chip design verification. A hardware model of interface circuitry implemented in a reconfigurable hardware modeling device associates dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device. The dispatch time information of a particular message includes information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design. The messages and the dispatch time information are sent to a traffic analysis device, which determines bandwidth information of ports of the circuit design based on the dispatch time information.
1. A method, comprising:
associating, by a hardware model of interface circuitry implemented in a reconfigurable hardware modeling device, dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, the dispatch time information of a particular message including information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design;
associating, by the hardware model of the interface circuitry, arrival time information with the messages when the messages are delivered to the hardware model of the circuit design, the arrival time information of a particular message including information about when, based on the model time reference, the particular message is delivered to the hardware model of the circuit design; and
sending the messages and the dispatch time information to a traffic analysis device, wherein the sending comprises sending the arrival time information along with the messages and the dispatch information to the traffic analysis device.
2. The method recited in claim 1 , wherein the associating the dispatch time information comprises:
inserting the dispatch time information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages.
3. The method recited in claim 1 , further comprising:
determining, by the message analysis device, bandwidth information of ports of the circuit design based on the dispatch time information and latency information based on the arrival time information and the dispatch time information.
4. The method recited in claim 1 , wherein the associating arrival time information with the messages comprises:
inserting the arrival time information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages.
5. The method recited in claim 1 , wherein the hardware model of the interface circuitry converts the messages from transaction-level messages to signal-level messages before delivering the messages to the hardware model of the circuit design and converts the messages from signal-level messages to transaction-level messages before sending the messages to the traffic analysis device.
6. The method recited in claim 1 , wherein the reconfigurable hardware modeling device is a hardware-based emulator or an FPGA-based prototyping device.
7. The method recited in claim 1 , wherein the circuit design is a design for a network switch, a router, a network processor, or a network gateway.
8. The method recited in claim 1 , wherein the traffic analysis device is implemented at least in part by a network traffic tool, the network traffic tool being implemented by a virtual machine running on a computer.
9. The method recited in claim 1 , wherein the model time reference is provided at least in part by a multi-bit register in the reconfigurable hardware modeling device.
10. One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to generate bitstreams for programming a reconfigurable hardware modeling device to implement circuitry hardware models, the circuitry hardware models comprising:
a hardware model of a circuit design, and
a hardware model of interface circuitry configurable to:
associate dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, the dispatch time information of a particular message including information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design; and
associate arrival time information with the messages when the messages are delivered to the hardware model of the circuit design, the arrival time information of a particular message including information about when, based on the model time reference, the particular message is delivered to the hardware model of the circuit design, wherein the messages, the arrival time information and the dispatch information are sent to a traffic analysis device.
11. The one or more non-transitory computer-readable media recited in claim 10 , wherein the association of the dispatch time information with the messages comprises:
inserting the dispatch time information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages.
12. The one or more non-transitory computer-readable media recited in claim 10 , wherein the traffic analysis device determines bandwidth information of ports of the circuit design based on the dispatch time information and determines latency information based on the arrival time information and the dispatch time information.
13. The one or more non-transitory computer-readable media recited in claim 10 , wherein the association of the arrival time information with the messages comprises:
inserting the arrival time information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages.
14. The one or more non-transitory computer-readable media recited in claim 10 , wherein the hardware model of the interface circuitry converts the messages from transaction-level messages to signal-level messages before delivering the messages to the hardware model of the circuit design and converts the messages from signal-level messages to transaction-level messages before sending the messages to the traffic analysis device.
15. The one or more non-transitory computer-readable media recited in claim 10 , wherein the reconfigurable hardware modeling device is a hardware-based emulator or an FPGA-based prototyping device.
16. The one or more non-transitory computer-readable media recited in claim 10 , wherein the circuit design is a design for a network switch, a router, a network processor, or a network gateway.
17. The one or more non-transitory computer-readable media recited in claim 10 , wherein the traffic analysis device is implemented at least in part by a network traffic tool, the network traffic tool being implemented by a virtual machine running on a computer.
18. The one or more non-transitory computer-readable media recited in claim 10 , wherein the model time reference is provided at least in part by a multi-bit register in the reconfigurable hardware modeling device.
19. A reconfigurable hardware modeling device programmed to implement circuitry hardware models, the circuitry hardware models comprising:
a hardware model of a circuit design, and
a hardware model of interface circuitry configurable to:
associate dispatch time information with messages when the messages are dispatched by a hardware model of a circuit design implemented in the reconfigurable hardware modeling device, the dispatch time information of a particular message including information about when, based on a model time reference provided in the reconfigurable hardware modeling device, the particular message is dispatched by the hardware model of the circuit design; and
associate arrival time information with the messages when the messages are delivered to the hardware model of the circuit design, the arrival time information of a particular message including information about when, based on the model time reference, the particular message is delivered to the hardware model of the circuit design, wherein the messages, the arrival time information and the dispatch information are sent to a traffic analysis device.
20. The reconfigurable hardware modeling device recited in claim 19 , wherein the association of the dispatch time information with the messages comprises:
inserting the dispatch time information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages.
21. The reconfigurable hardware modeling device recited in claim 19 , wherein the traffic analysis device determines bandwidth information of ports of the circuit design based on the dispatch time information and determines latency information based on the arrival time information and the dispatch time information.
22. The reconfigurable hardware modeling device recited in claim 19 , wherein the association of the arrival time information with the messages comprises:
inserting the arrival time information of each of the messages in a metadata field of or a data field of the each of the messages or in special messages.
23. The reconfigurable hardware modeling device recited in claim 19 , wherein the hardware model of the interface circuitry converts the messages from transaction-level messages to signal-level messages before delivering the messages to the hardware model of the circuit design and converts the messages from signal-level messages to transaction-level messages before sending the messages to the traffic analysis device.
24. The reconfigurable hardware modeling device recited in claim 19 , wherein the reconfigurable hardware modeling device is a hardware-based emulator or an FPGA-based prototyping device.
25. The reconfigurable hardware modeling device recited in claim 19 , wherein the circuit design is a design for a network switch, a router, a network processor, or a network gateway.
26. The reconfigurable hardware modeling device recited in claim 19 , wherein the traffic analysis device is implemented at least in part by a network traffic tool, the network traffic tool being implemented by a virtual machine running on a computer.
27. The reconfigurable hardware modeling device recited in claim 19 , wherein the model time reference is provided at least in part by a multi-bit register in the reconfigurable hardware modeling device.