High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate
View Patent ↗Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.
1. One or more computer-readable storage media storing computer-executable instructions which when executed by a computer cause the computer to perform a method, the method comprising:
receiving layout information indicative of at least signal-wire segments in a circuit design;
identifying at least one signal-wire segment having a length that exceeds a transverse distance to a nearest neighboring return path by more than a threshold amount;
performing a first impedance extraction technique for the identified at least one signal-wire segment, the first impedance extraction technique generating a first representation of impedance effects in the circuit design; and
performing a second impedance extraction technique for other signal-wire segments in the circuit design, the second impedance extraction technique generating a second representation of the impedance effects in the circuit design,
wherein the first impedance extraction technique and the second impedance extraction technique both account for electrical effects caused by a multi-layer substrate, and
wherein the first impedance extraction technique is computationally more efficient but less accurate than the second impedance extraction technique.
2. The one or more computer-readable media of claim 1 , wherein the method further comprises merging the first representation with the second representation to generate a complete representation of the impedance effects in the circuit design.
3. The one or more computer-readable media of claim 1 , wherein the first impedance extraction technique uses an approximation of a two-dimensional Green's function and the second impedance extraction technique uses an approximation of a three-dimensional Green's function.
4. The one or more computer-readable media of claim 1 , wherein the first impedance extraction technique and the second impedance extraction technique do not represent the multi-layer substrate as a plurality of filaments.
5. The one or more computer-readable media of claim 1 , wherein the threshold amount is 20 times the transverse distance to the nearest neighboring return path.
6. The one or more computer-readable media of claim 1 , wherein the identified at least one signal-wire segment is part of a bundle.
7. A computer-implemented method, comprising:
receiving layout information indicative of at least signal-wire segments in a circuit design;
identifying at least one signal-wire segment having a length that exceeds a transverse distance to a nearest neighboring return path by more than a threshold amount;
performing a first impedance extraction technique for the identified at least one signal-wire segment, the first impedance extraction technique generating a first representation of impedance effects in the circuit design; and
performing a second impedance extraction technique for other signal-wire segments in the circuit design, the second impedance extraction technique generating a second representation of the impedance effects in the circuit design,
wherein the first impedance extraction technique and the second impedance extraction technique both account for electrical effects caused by a multi-layer substrate, and
wherein the first impedance extraction technique is computationally more efficient but less accurate than the second impedance extraction technique.
8. The method of claim 7 further comprising:
merging the first representation with the second representation to generate a complete representation of the impedance effects in the circuit design.
9. The method of claim 7 , wherein the first impedance extraction technique uses an approximation of a two-dimensional Green's function and the second impedance extraction technique uses an approximation of a three-dimensional Green's function.
10. The method of claim 7 , wherein the first impedance extraction technique and the second impedance extraction technique do not represent the multi-layer substrate as a plurality of filaments.
11. The method of claim 7 , wherein the threshold amount is 20 times the transverse distance to the nearest neighboring return path.
12. The method of claim 7 , wherein the identified at least one signal-wire segment is part of a bundle.
13. A system comprising:
a processor; and
a computer-readable medium having stored thereon a plurality of instructions which, when executed, cause the processor to perform a method, the method comprising:
receiving layout information indicative of at least signal-wire segments in a circuit design;
identifying at least one signal-wire segment having a length that exceeds a transverse distance to a nearest neighboring return path by more than a threshold amount;
performing a first impedance extraction technique for the identified at least one signal-wire segment, the first impedance extraction technique generating a first representation of impedance effects in the circuit design; and
performing a second impedance extraction technique for other signal-wire segments in the circuit design, the second impedance extraction technique generating a second representation of the impedance effects in the circuit design,
wherein the first impedance extraction technique and the second impedance extraction technique both account for electrical effects caused by a multi-layer substrate, and
wherein the first impedance extraction technique is computationally more efficient but less accurate than the second impedance extraction technique.
14. The system of claim 13 , the method further comprising:
merging the first representation with the second representation to generate a complete representation of the impedance effects in the circuit design.
15. The system of claim 13 , wherein the first impedance extraction technique uses an approximation of a two-dimensional Green's function and the second impedance extraction technique uses an approximation of a three-dimensional Green's function.
16. The system of claim 13 , wherein the first impedance extraction technique and the second impedance extraction technique do not represent the multi-layer substrate as a plurality of filaments.
17. The system of claim 13 , wherein the threshold amount is 20 times the transverse distance to the nearest neighboring return path.
18. The system of claim 13 , wherein the identified at least one signal-wire segment is part of a bundle.