High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate
View Patent ↗Embodiments of methods, apparatus, and systems for extracting impedance for a circuit design are disclosed herein. Some of the disclosed embodiments are computationally efficient and can accurately compute the frequency-dependent impedance of VLSI interconnects and/or intentional inductors in the presence of multi-layer conductive substrates. In certain embodiments, the resulting accuracy and CPU time reduction are a result of a Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the distances relevant to VLSI interconnects and intentional inductors.
1. One or more computer-readable storage media storing computer-executable instructions which when executed by a computer cause the computer to perform a method, the method comprising:
receiving semiconductor chip design information, the semiconductor chip design information comprising substrate profile information for a substrate over or under which a circuit design is to be implemented;
generating a representation of electrical effects of the substrate at an operating frequency of interest, the representation representing the electrical effects of the substrate as a combined effect of a linear combination of exponentials, wherein the representation is computed by the equation:
g
N
(
λ
)
≈
∑
k
=
1
K
β
k
ⅇ
-
α
k
(
λ
γ
1
)
where α k and β k are real numbers; and
storing the representation of the electrical effects of the substrate.
2. The one or more computer-readable media of claim 1 , wherein each of the exponentials includes unknown parameters, and wherein the method further comprises computing values of the unknown parameters using a non-linear least squares fitting technique.
3. The one or more computer-readable media of claim 1 , wherein the exponentials correspond to vector potentials caused by source magnetic dipoles.
4. The one or more computer-readable media of claim 1 , wherein the substrate has multiple layers.
5. The one or more computer-readable media of claim 1 , wherein the method further comprises repeating the acts of generating and storing for multiple other operating frequencies of interest.
6. The one or more computer-readable media of claim 1 , wherein the method further comprises:
receiving layout information indicative of at least signal-wire segments in a circuit design;
computing impedance values for the signal-wire segments in the circuit design using the representation of the electrical effects of the substrate at the operating frequency of interest; and
storing the impedance values for the signal-wire segments in the circuit design.
7. A computer-implemented method, comprising:
receiving semiconductor chip design information, the semiconductor chip design information comprising substrate profile information for a substrate over or under which a circuit design is to be implemented;
generating a representation of electrical effects of the substrate at an operating frequency of interest, the representation representing the electrical effects of the substrate as a combined effect of a linear combination of exponentials, the representation further having coefficients that are real numbers and not complex numbers; and
storing the representation of the electrical effects of the substrate.
8. The method of claim 7 , wherein each of the exponentials includes unknown parameters, and wherein the method further comprises computing values of the unknown parameters using a non-linear least squares fitting technique.
9. The method of claim 7 , wherein the exponentials correspond to vector potentials caused by source magnetic dipoles.
10. The method of claim 7 , wherein the substrate has multiple layers.
11. The method of claim 7 , wherein the method further comprises repeating the acts of generating and storing for multiple other operating frequencies of interest.
12. The method of claim 7 , wherein the method further comprises:
receiving layout information indicative of at least signal-wire segments in a circuit design;
computing impedance values for the signal-wire segments in the circuit design using the representation of the electrical effects of the substrate at the operating frequency of interest; and
storing the impedance values for the signal-wire segments in the circuit design.
13. A system, comprising:
means for receiving semiconductor chip design information, the semiconductor chip design information comprising substrate profile information for a substrate over or under which a circuit design is to be implemented; and
means for generating a representation of electrical effects of the substrate at an operating frequency of interest, the representation representing the electrical effects of the substrate as a combined effect of a linear combination of exponentials, wherein the representation is computed by the equation:
g
N
(
λ
)
≈
∑
k
=
1
K
β
k
ⅇ
-
α
k
(
λ
γ
1
)
where α k and β k are real numbers.
14. One or more computer-readable storage media storing computer-executable instructions which when executed by a computer cause the computer to perform a method, the method comprising:
receiving semiconductor chip design information, the semiconductor chip design information comprising substrate profile information for a substrate over or under which a circuit design is to be implemented; and
generating a representation of electrical effects of the substrate at an operating frequency of interest, the representation representing the electrical effects of the substrate as a combined effect of a linear combination of exponentials, the representation further having coefficients that are real numbers and not complex numbers.