Multiple-level memory with analog read
View Patent ↗A memory circuit includes a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein, and a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells. The circuit further includes multiple sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge. An analog multiplexer is connected to the sense amplifiers. The analog multiplexer is operative to receive the respective analog signals from the sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the sense amplifiers.
1. A memory circuit, comprising:
a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein;
a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells;
a plurality of sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge; and
an analog multiplexer connected to the plurality of sense amplifiers, the analog multiplexer being operative to receive the respective analog signals from the plurality of sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the plurality of sense amplifiers.
2. The circuit of claim 1 , wherein the output signal generated by the analog multiplexer comprises a continuous analog signal representative of sequential reads from at least a subset of the plurality of memory cells.
3. The circuit of claim 1 , wherein the analog multiplexer is operative to convert the electric charge stored in the selected memory cell to a proportionate analog voltage representative of the stored electric charge.
4. The circuit of claim 1 , wherein at least one of the plurality of sense amplifiers comprises an analog voltage buffer.
5. The circuit of claim 1 , wherein the analog multiplexer comprises a plurality of transmission gates, each transmission gate having a first input connected to a corresponding one of the sense amplifiers, a second input for receiving a control signal, and an output, respective outputs of the transmission gates being connected together and forming an output of the analog multiplexer, each transmission gate being operative to electrically couple the first input of the transmission gate to the output of the transmission gate as a function of the control signal supplied to the second input of the transmission gate.
6. The circuit of claim 1 , further comprising error correction circuitry connected to the analog multiplexer, the error correction circuitry being operative to correct at least one bit error detected in the analog output signal.
7. The circuit of claim 1 , wherein the magnitude of the analog output signal is representative of electric charge stored in a sequence of memory cells that are not physically adjacent to one another.
8. The circuit of claim 1 , further comprising a controller connected to the analog multiplexer and operative to control a sequence of the respective analog signals from the plurality of sense amplifiers represented in the analog output signal.
9. The circuit of claim 1 , wherein the analog multiplexer is operative to combine the respective analog signals from the plurality of sense amplifiers in at least one of an ascending and a descending numerical sequence to generate the analog output signal.
10. An integrated circuit including at least one memory circuit, the at least one memory circuit comprising:
a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein;
a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells;
a plurality of sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge; and
an analog multiplexer connected to the plurality of sense amplifiers, the analog multiplexer being operative to receive the respective analog signals from the plurality of sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the plurality of sense amplifiers.
11. The integrated circuit of claim 10 , wherein the output signal generated by the analog multiplexer comprises a continuous analog signal representative of sequential reads from at least a subset of the plurality of memory cells.
12. The integrated circuit of claim 10 , wherein the analog multiplexer is operative to convert the electric charge stored in the selected memory cell to a proportionate analog voltage representative of the stored electric charge.
13. The integrated circuit of claim 10 , wherein at least one of the plurality of sense amplifiers comprises an analog voltage buffer.
14. The integrated circuit of claim 10 , wherein the analog multiplexer comprises a plurality of transmission gates, each transmission gate having a first input connected to a corresponding one of the sense amplifiers, a second input for receiving a control signal, and an output, respective outputs of the transmission gates being connected together and forming an output of the analog multiplexer, each transmission gate being operative to electrically couple the first input of the transmission gate to the output of the transmission gate as a function of the control signal supplied to the second input of the transmission gate.
15. The integrated circuit of claim 10 , wherein the at least one memory circuit further comprises error correction circuitry connected to the analog multiplexer, the error correction circuitry being operative to correct at least one bit error detected in the analog output signal.
16. The integrated circuit of claim 10 , wherein the magnitude of the analog output signal is representative of electric charge stored in a sequence of memory cells in the at least one memory circuit that are not physically adjacent to one another.
17. The integrated circuit of claim 10 , wherein the at least one memory circuit further comprises a controller connected to the analog multiplexer and operative to control a sequence of the respective analog signals from the plurality of sense amplifiers represented in the analog output signal.
18. The integrated circuit of claim 10 , wherein the analog multiplexer is operative to combine the respective analog signals from the plurality of sense amplifiers in at least one of an ascending and a descending numerical sequence to generate the analog output signal.
19. A method of reading a memory circuit including a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein, the method comprising the steps of:
for each of at least a subset of the memory cells, converting an electric charge stored in at least a selected one of the memory cells to a proportionate analog signal representative of the stored electric charge, the electric charge stored in the selected memory cell being indicative of a state of the selected memory cell;
combining a plurality of analog signals from a plurality of corresponding memory cells in the memory circuit to generate an analog output signal, the analog output signal having a magnitude which varies in time as a function of the respective analog signals from the plurality of corresponding memory cells; and
sampling the analog output signal at distinct times representative of a sequence of the respective analog signals from the plurality of corresponding memory cells.
20. An electronic system, comprising:
at least one integrated circuit including at least one embedded memory circuit, the at least one embedded memory circuit comprising:
a plurality of memory cells, each of the memory cells being operative to store multiple bits of data therein;
a plurality of column lines and row lines coupled to the memory cells for selectively accessing the memory cells;
a plurality of sense amplifiers, each of the sense amplifiers being connected to a corresponding one of the column lines and being operative to detect an electric charge stored in a selected one of the memory cells coupled to the corresponding column line and to generate an analog signal indicative of the stored electric charge; and
an analog multiplexer connected to the plurality of sense amplifiers, the analog multiplexer being operative to receive the respective analog signals from the plurality of sense amplifiers and to generate an analog output signal having a magnitude which varies in time as a function of the respective analog signals from the plurality of sense amplifiers.