Methods of forming memory cells, and methods of forming programmed memory cells
View Patent ↗In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.
1. A method of forming a programmed memory cell, comprising:
forming a transistor which includes a transistor gate spaced from a channel region by a gate dielectric, and which includes a source region on one side of the channel region and a drain region on an opposing side of the channel region from the source region; wherein the channel region comprises phase change material adjacent the drain region;
forming an inversion layer within the channel region adjacent the gate dielectric, the inversion layer having a pinch-off region within the phase change material adjacent the drain region; and
utilizing hot carriers within the pinch-off region to change a phase within the phase change material.
2. The method of claim 1 wherein the change in phase decreases crystallinity of the phase change material.
3. The method of claim 1 wherein the change in phase increases crystallinity of the phase change material.
4. The method of claim 1 wherein the hot carriers are electrons.
5. The method of claim 1 wherein the hot carriers are holes.
6. The method of claim 1 wherein the phase change material extends throughout an entirety of the channel region.
7. The method of claim 1 wherein the channel region primarily comprises non-phase change semiconductor material, and comprises the phase change material only adjacent the drain region.
8. The method of claim 1 wherein:
the gate dielectric is formed over a silicon-containing substrate;
the transistor gate has a pair of opposing sidewalls;
a recess is formed in the substrate adjacent one of the sidewalls;
the phase change material is provided within the recess;
a pair of spacers are formed along the opposing sidewalls of the gate; and
dopant is implanted into the substrate while using the gate and spacers as a mask to form the source and drain regions within the substrate.
9. The method of claim 1 wherein:
the transistor gate has a pair of opposing sidewalls, and the gate dielectric material is formed over a semiconductor base;
a pair of sidewall spacers are formed along the pair of opposing sidewalls;
a mask is formed over the base along one side of the transistor gate, and not over a region of the base along another side of the transistor gate in opposing relation to said one side;
an opening is etched into said region of the base, with the opening extending to under one of the sidewall spacers;
the phase change material is provided within the opening and under said one of the sidewall spacers to partially fill the opening;
after the phase change material is provided within the opening, semiconductor material is epitaxially grown within the opening; and
the drain region is formed to extend into the epitaxially-grown semiconductor material.
10. The method of claim 1 wherein:
the gate dielectric is formed over a silicon-containing substrate;
the transistor gate has a pair of opposing sidewalls;
a pair of recesses are formed in the substrate adjacent the sidewalls;
the phase change material is provided within the recesses;
a pair of spacers are formed along the opposing sidewalls of the transistor gate and directly over the phase change material within the recesses; and
dopant is implanted into the substrate while using the transistor gate and spacers as a mask, with the implanted dopant forming the source and drain regions within the substrate.
11. The method of claim 1 wherein:
the gate dielectric is formed over a silicon-containing substrate;
the transistor gate has a pair of opposing sidewalls;
a pair of spacers are formed along the opposing sidewalls of the transistor gate, with the spacers comprising sacrificial material vertically sandwiched between non-sacrificial material;
the sacrificial material is removed to form openings exposing regions of the substrate;
the exposed regions of the substrate are etched to form recesses in the substrate;
the phase change material is provided within the recesses;
the openings are filled with non-sacrificial material; and
dopant is implanted into the substrate to form the source and drain regions.
12. The method of claim 11 wherein:
the non-sacrificial material comprises phase change material; and
the forming the phase change material within the recesses and the filling the openings with the non-sacrificial material occur together with the phase change material being formed within the recesses and then filling the openings.