Semiconductor package configuration with improved lead portion arrangement
View Patent ↗A semiconductor device with improved reliability is provided. The semiconductor device in a QFN package configuration has a semiconductor chip mounted on a tab, leads which are alternately arranged around the tab and electrically connected to the electrodes of the semiconductor chip via bonding wires, and an encapsulating resin portion for encapsulating therein the semiconductor chip and the bonding wires. The lower exposed surfaces of the leads are exposed at the outer peripheral portion of the back surface of the encapsulating resin portion to form external terminals. The lower exposed surfaces of the leads are exposed at the portion of the back surface of the encapsulating resin portion which is located inwardly of the lower exposed surface of the leads to also form external terminals. The cut surfaces of the leads are exposed at the cut surfaces of the encapsulating resin portion, while the upper exposed surfaces of the leads are exposed from the portion of the encapsulating resin portion which is proximate to the cut surfaces thereof. Each of the upper exposed surfaces of the leads has a width smaller than the width of each of the lower exposed surfaces thereof.
1. A semiconductor device comprising:
a chip mounting portion;
a semiconductor chip mounted over said chip mounting portion, said semiconductor chip having a main surface and a plurality of electrodes formed on said main surface thereof;
a plurality of suspension lead portions integrated with said chip mounting portion, respectively;
a plurality of lead portions arranged around said chip mounting portion, each of said plurality of lead portions including one end portion facing to said chip mounting portion and an other end portion opposing to said one end portion, said plurality of lead portions including a first lead portion and a second lead portion arranged next to said first lead portion;
a plurality of wires electrically connecting said plurality of electrodes of said semiconductor chip with said plurality of lead portions, respectively; and
an encapsulating resin portion sealing said semiconductor chip and said plurality of wires, said encapsulating resin including an upper surface, a lower surface opposing to said upper surface, and side surfaces between said upper surface and said lower surface;
wherein said first lead portion includes a first lower exposed surface exposed from said lower surface of said encapsulating resin at a peripheral portion of said encapsulating resin, and a first upper exposed surface opposing to said first lower exposed surface and exposed from said upper surface of said encapsulating resin at said peripheral portion of said encapsulating resin;
wherein said second lead portion includes a second lower exposed surface arranged at said chip mounting portion side at a location different than said first lower exposed surface and exposed from said lower surface of said encapsulating resin, and a second upper exposed surface arranged at an opposite side of said second lower exposed surface and exposed from said upper surface of said encapsulating resin at said peripheral portion of said encapsulating resin; and
wherein a width of said first lower exposed surface is larger than a width of said first upper exposed surface.
2. The semiconductor device according to claim 1 , wherein a dimension of said chip mounting portion is smaller than a corresponding dimension of said semiconductor chip.
3. The semiconductor device according to claim 1 , wherein said first lead portion includes a first cut surface exposed from each of said side surfaces of said encapsulating resin, and
wherein at said first cut surface, said width of said first lower exposed surface is larger than said width of said first upper exposed surface.
4. The semiconductor device according to claim 1 , wherein a dimension of said first lower exposed surface is larger than a corresponding dimension of said second lower exposed surface.
5. The semiconductor device according to claim 1 , wherein a thickness of said one end portion of said first lead portion is thinner than a thickness of said other end portion of said first lead portion.
6. The semiconductor device according to claim 1 , wherein a thickness of said one end portion of said second lead portion is thicker than a thickness of said other end portion of said second lead portion.
7. The semiconductor device according to claim 1 , wherein a plated layer is formed on said first lower exposed surface, said first upper exposed surface, said second lower exposed surface and said second upper exposed surface.