Memory device and method thereof
View Patent ↗A device, and corresponding method, includes a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent discharge time can be achieved at a sense node of a sense amplifier.
1. A method comprising:
charging a sense node of a first sense amplifier during a pre-charge portion of a first time period;
generating a first gate signal based upon a first temperature;
discharging the sense node based upon the first gate signal during the first time period for an amount of time; and
determining, during the first time period, a first logic state based upon a first charge at the sense node remaining after discharging the sense node based upon the second gate signal for the amount of time.
2. The method of claim 1 wherein the first amount of time is substantially independent of temperature.
3. The method of claim 1 further comprising:
charging the sense node of the first sense amplifier during a pre-charge portion of a second time period;
generating a second gate signal based upon a second temperature;
discharging the sense node based upon the second gate signal during the second time period for an amount of time;
determining, during the second period, a second logic state based upon a second charge at the sense node remaining after discharging the sense node based upon the second gate signal for the amount of time.
4. The method of claim 3 wherein in response to the second temperature being greater than the first temperature the second gate signal will have a voltage less than a voltage of the first gate signal, and in response to the second temperature being less than the first temperature the second gate signal will have a voltage greater than a voltage of the first gate signal.
5. The method of claim 3 wherein the amount of time during the first time period is substantially the same as the amount of time during the second time period when the second temperature is substantially different than the first temperature.
6. The method of claim 1 wherein the first temperature is the temperature at a first location of an integrated circuit, and claim 1 further comprises:
charging a sense node of a second sense amplifier during the pre-charge portion of the first time period;
generating a second gate signal based upon a second temperature at a second location of the integrated circuit;
discharging the sense node of the second sense amplifier based upon the second gate signal during the first time period for the amount of time;
determining, during the first time period, a second logic state based upon a second charge at the sense node of the second sense amplifier, the second charge remaining after discharging the sense node of the second sense amplifier based upon the second gate signal for the amount of time.
7. The method of claim 6 wherein in the amount of time during the first time period is substantially the same as the amount of time during the second time period when the second temperature is substantially different than the first temperature.
8. The method of claim 1 wherein the first temperature is the temperature during the first time period.
9. The method of claim 1 , wherein discharging further comprises discharging the sense node through a NAND flash.
10. A memory device comprising:
a temperature dependent signal generator comprising a first terminal to receive a reference signal, a transistor comprising a first current electrode, a second current electrode, and a control electrode electrically connected to the first current electrode, the first current electrode selectively electrically connected to a second terminal of the temperature dependent signal generator to provide a signal that is temperature dependent; and
a sense amplifier comprising
a sense node,
a sense device comprising an input connected to the sense node and an output to provide a logic state based upon a signal at the sense node, and
a transistor comprising a first current electrode electrically connected to the sense node, a second current electrode electrically connected to a bit line of a memory array, and a control gate electrically connected to the second terminal of the temperature dependent voltage reference generator.
11. The device of claim 10 wherein the sense amplifier is a first sense amplifier, and the bit line is a first bit line, the device of claim 1 further comprising:
a second sense amplifier comprising
a sense node,
a sense device comprising an input connected to the sense node and an output to provide a logic state based upon a signal at the sense node, and
a transistor comprising a first current electrode electrically connected to the sense node, a second current electrode electrically connected to a second bit line of the memory array, and a control gate electrically connected to the second terminal of the temperature dependent voltage reference generator.
12. The device of claim 10 further comprising a NAND string connected to the bit line.
13. The device of claim 10 wherein the temperature dependent signal generator is a first temperature dependent signal generator, the sense amplifier is a first sense amplifier, and the bit line is a first bit line, the device of claim 1 further comprising:
a second temperature dependent signal generator comprising a first terminal to receive the reference signal, and a second terminal to provide a signal that is temperature dependent; and
a second sense amplifier comprising
a sense node,
a sense device comprising an input connected to the sense node and an output to provide a logic state based upon a signal at the sense node, and
a transistor comprising a first current electrode electrically connected to the sense node, a second current electrode electrically connected to a second bit line of the memory array, and a control gate electrically connected to the second terminal of the second temperature dependent voltage reference generator.
14. The device of claim 13 further comprising a NAND string connected to the bit line.
15. The device of claim 10 , wherein the temperature dependent signal generator comprises a transistor selectively electrically connected to the second terminal to provide the signal that is temperature dependent, the transistor of the temperature dependent signal generator being matched to the transistor of the sense amplifier.
16. The device of claim 15 , wherein temperature dependent signal generator further comprises:
a fixed signal generator comprising a terminal electrically connected to the second current electrode of the transistor of the temperature dependent signal generator to provide a fixed signal reference; and
a signal reference comprising a terminal electrically connected to the first current electrode.
17. The device of claim 16 further comprising a NAND string connected to the bit line.
18. The device of claim 16 further comprising:
a pre-charge node to provide charge to the sense node in response to the device being in a pre-charge state, and electrically connected to the fixed signal generator, the fixed signal reference to be based upon a signal at the pre-charge node.
19. A memory device comprising:
a temperature dependent signal generator comprising a first terminal to receive a reference signal, a transistor comprising a first current electrode, a second current electrode, and a control electrode, and a differential amplifier comprising a first input, a second input electrically connected to the second electrode of the transistor, and an output electrically connected to the control electrode of the transistor, the output of the differential amplifier selectively electrically connected to a second terminal of the temperature dependent signal generator to provide a signal that is temperature dependent;
a sense amplifier comprising
a sense node,
a sense device comprising an input connected to the sense node and an output to provide a logic state based upon a signal at the sense node, and
a transistor comprising a first current electrode electrically connected to the sense node, a second current electrode electrically connected to a bit line of a memory array, and a control gate electrically connected to the second terminal of the temperature dependent voltage reference generator.
20. A memory comprising:
a first temperature dependent signal generator comprising a first terminal to receive a reference signal, and a second terminal to provide a signal that is temperature dependent; and
a first sense amplifier comprising
a sense node,
a sense device comprising an input connected to the sense node and an output to provide a logic state based upon a signal at the sense node, and
a transistor comprising a first current electrode electrically connected to the sense node, a second current electrode electrically connected to a first bit line of a memory array, and a control gate electrically connected to the second terminal of the first temperature dependent voltage reference generator;
a second temperature dependent signal generator comprising a first terminal to receive the reference signal, and a second terminal to provide a signal that is temperature dependent; and
a second sense amplifier comprising
a sense node,
a sense device comprising an input connected to the sense node and an output to provide a logic state based upon a signal at the sense node, and
a transistor comprising a first current electrode electrically connected to the sense node, a second current electrode electrically connected to a second bit line of the memory array, and a control gate electrically connected to the second terminal of the second temperature dependent voltage reference generator.