SEMICONDUCTOR DEVICE AND FABRICATION METHOD
The present invention provides an SOI device which has high breakdown voltage, wide stable operation range, good thermal dissipation, and high effective conductance and good frequency characteristics, and a method for fabricating the device. In a semiconductor device, a BOX region is formed on a part of a surface layer of a p substrate. The BOX region is formed around a point where a vertical line is dropped from the center of the gate structure portion, and isolates a drain region and an extended drain region from the p − substrate. The thickness of the drain region is in a 150 nm to 300 nm range, and the thickness of the BOX region is 150 nm or more.
1 . A semiconductor device, comprising:
a first conductive type high resistivity region;
a buried oxide region which is formed on a part of a surface layer of the high resistivity region;
a first conductive type first semiconductor region of which resistivity is lower than the high resistivity region, and which is formed on a part of the surface layer of the high resistivity region, so as to contact a side face and a part of a surface of the buried oxide region;
a gate electrode which is formed on a surface of the first semiconductor region via a gate insulation film;
a spacer region which is formed on a side face the gate electrode;
a second conductive type low resistivity drain region which is formed on a part of the surface of the buried oxide region so as to be isolated from the first semiconductor region and the high resistivity region, and aligned with the edge of the spacer region;
a second conductive type second semiconductor region which is formed on a part of the surface of the buried oxide region, so as to be isolated from the high resistivity region, contact the first semiconductor region and the low resistivity drain region, and aligned with the edge of the gate electrode at the low resistivity drain region side;
a first conductive type first low resistivity region which is formed on a part of the surface layer of the high resistivity region so as to be isolated from the first semiconductor region;
a second conductive type low resistivity source region which is formed on a part of the surface layer of the high resistivity region so as to contact the first semiconductor region and the first low resistivity region, and aligned with the edge of the gate electrode at the first low resistivity region side;
a first conductive type second low resistivity region which is formed so as to be aligned with the edge of the spacer region at the first low resistivity region side, and to be thicker than the low resistivity source region;
a first conductive type buried region which is formed so as to be aligned with the edges of the gate electrode at the low resistivity drain region side and at the first low resistivity region side;
a silicide region which is formed on a part of the surface layer of the low resistivity drain region and a part of the surface layer of the low resistivity source region;
an inter-layer insulation film which covers the gate electrode, the spacer region and the silicide region;
a drain electrode which contacts the low resistivity drain region and covers a part of the surface of the inter-layer insulation film; and
a source electrode which contacts the low resistivity source region and covers a part of the surface of the inter-layer insulation film, wherein
the thickness of the low resistivity drain region and the second semiconductor region is in a 150 nm to 300 nm range.
2 . The semiconductor device according to claim 1 , wherein the buried oxide region is formed of silicon dioxide, and the thickness of the buried oxide region is 400 nm or more.
3 . The semiconductor device according to claim 1 , wherein the buried oxide region is a SON (Silicon-ON-Nothing) layer, and the thickness of the buried oxide region is 150 nm or more.
4 . The semiconductor device according to claim 1 , wherein the thickness of the gate insulation film is thicker at the edge side of the gate electrode than at the center side of the gate electrode.
5 . A semiconductor device, comprising:
a first conductive type high resistivity region which is formed on a first conductive type low resistivity semiconductor substrate;
a buried oxide region which is formed on a part of a surface layer of the high resistivity region;
a first conductive type first semiconductor region of which resistivity is lower than the high resistivity region, and which is formed on a part of the surface layer of the high resistivity region, so as to contact a side face and a part of a surface of the buried oxide region;
a gate electrode which is formed on a surface of the first semiconductor region via a gate insulation film;
a spacer region which is formed on a side face of the gate electrode;
a second conductive type low resistivity drain region which is formed on a part of the surface of the buried oxide region so as to be isolated from the first semiconductor region and the high resistivity region, and aligned with the edge of the spacer region;
a second conductive type second semiconductor region which is formed on a part of the surface of the buried oxide region so as to be isolated from the high resistivity region, contact the first semiconductor region and the low resistivity drain region, and aligned with the edge of the gate electrode at the low resistivity drain region side;
a first conductive type first low resistivity region which is formed on a part of the surface layer of the high resistivity region so as to be isolated from the first semiconductor region;
a second conductive type low resistivity source region which is formed on a part of the surface layer of the high resistivity region so as to contact the first semiconductor region and the first low resistivity region, and aligned with the edge of the gate electrode at the first low resistivity region side;
a first conductive type second low resistivity region which is formed so as to be aligned with the edge of the spacer region at the first low resistivity region side, and to be thicker than the low resistivity source region;
a first conductive type buried region which is formed so as to be aligned with the edges of the gate electrode at the low resistivity drain region side and at the first low resistivity region side;
a first conductive type third low resistivity region which is formed in a trench which penetrates through the first low resistivity region and the high resistivity region, and reaches the low resistivity semiconductor substrate;
a first conductive type fourth low resistivity region which covers a periphery of the third low resistivity region;
a silicide region which is formed on a part of the surface layer of the low resistivity drain region and a part of the surface layer of the low resistivity source region;
an inter-layer insulation film which covers the gate electrode, the spacer region and the silicide region;
a drain electrode which contacts the low resistivity drain region and covers a part of the surface of the inter-layer insulation film; and
a source electrode which contacts the low resistivity source region and covers a part of the surface of the inter-layer insulation film, wherein
the thickness of the low resistivity drain region and the second semiconductor region is in a 150 nm to 300 nm range.
6 . The semiconductor device according to claim 5 , wherein the buried oxide region is formed of silicon dioxide, and the thickness of the buried oxide region is 400 nm or more.
7 . The semiconductor device according to claim 5 , wherein the buried oxide region is a SON (Silicon-ON-Nothing) layer, and the thickness of the buried oxide region is 150 nm or more.
8 . The semiconductor device according to claim 5 , wherein the thickness of the gate insulation film is thicker at the edge side of the gate electrode than at the center side of the gate electrode.
9 . A semiconductor device, comprising:
a first conductive type high resistivity region which is formed on a first conductive type low resistivity semiconductor substrate;
a buried oxide region which is formed on a part of a surface layer of the high resistivity region;
a first conductive type first semiconductor region of which resistivity is lower than the high resistivity region, and which is formed on a part of the surface layer of the high resistivity region, so as to contact a side face and a part of a surface of the buried oxide region;
a gate electrode which is formed on a surface of the first semiconductor region via a gate insulation film;
a spacer region which is formed on a side face of the gate electrode;
a second conductive type low resistivity drain region which is formed on a part of the surface of the buried oxide region, so as to be isolated from the first semiconductor region and the high resistivity region, and aligned with the edge of the spacer region;
a second conductive type second semiconductor region which is formed on a part of the surface of the buried oxide region, so as to be isolated from the high resistivity region, contact the first semiconductor region and the low resistivity drain region, and aligned with the edge of the gate electrode at the low resistivity drain region side;
a first conductive type first low resistivity region which is formed so as to be isolated from the first semiconductor region, and penetrate through the high resistivity region and reach the low resistivity semiconductor substrate;
a second conductive type low resistivity source region which is formed on a part of the surface layer of the high resistivity region, so as to contact the first semiconductor region and the first low resistivity region, and aligned with the edge of the gate electrode at the first low resistivity region side;
a first conductive type second low resistivity region which is formed so as to be aligned with the edge of the spacer region at the first low resistivity region side, and to be thicker than the low resistivity source region;
a first conductive type buried region which is formed so as to be aligned with the edges of the gate electrode at the low resistivity drain region side and at the first low resistivity region side;
a silicide region which is formed on a part of the surface layer of the low resistivity drain region and a part of the surface layer of the low resistivity source region;
an inter-layer insulation film which covers the gate electrode, the spacer region and the silicide region;
a drain electrode which contacts the low resistivity drain region and covers a part of the surface of the inter-layer insulation film; and
a source electrode which contacts the low resistivity source region and covers a part of the surface of the inter-layer insulation film, wherein
the thickness of the low resistivity drain region and the second semiconductor region is in a 150 nm to 300 nm range.
10 . The semiconductor device according to claim 9 , wherein the buried oxide region is formed of silicon dioxide, and the thickness of the buried oxide region is 400 nm or more.
11 . The semiconductor device according to claim 9 , wherein the buried oxide region is a SON (Silicon-ON-Nothing) layer, and the thickness of the buried oxide region is 150 nm or more.
12 . The semiconductor device according to claim 9 , wherein the thickness of the gate insulation film is thicker at the edge side of the gate electrode than at the center side of the gate electrode.
13 . A semiconductor device, comprising:
a first conductive type high resistivity region;
a buried oxide region which is formed on a part of a surface layer of the high resistivity region;
a first conductive type first semiconductor region of which resistivity is lower than the high resistivity region, and which is formed on a part of the surface layer of the high resistivity region, so as to contact a side face and a part of a surface of the buried oxide region;
a gate electrode which is formed on a surface of the first semiconductor region via a gate insulation film;
a second conductive type low resistivity drain region which is formed on a part of the surface of the buried oxide region, so as to be isolated from the first semiconductor region and the high resistivity region;
a second conductive type second semiconductor region which is formed on a part of the surface of the buried oxide region, so as to be isolated from the high resistivity region and contact the first semiconductor region and the low resistivity drain region;
a first conductive type first low resistivity region which is formed on a part of the surface layer of the high resistivity region, so as to be isolated from the first semiconductor region;
a second conductive type low resistivity source region which is formed on a part of the surface layer of the high resistivity region, so as to contact the first semiconductor region and the first low resistivity region;
a first conductive type second low resistivity region which is formed so as to be aligned with the edge of a spacer region at the first low resistivity region side, and to be thicker than the low resistivity source region;
an inter-layer insulation film which covers the gate electrode;
a drain electrode which contacts the low resistivity drain region and covers a part of the surface of the inter-layer insulation film; and
a source electrode which contacts the low resistivity source region and covers a part of the surface of the inter-layer insulation film, wherein
the buried oxide region extends to a position overlapping the gate electrode.
14 . The semiconductor device according to claim 13 , wherein the buried oxide region is formed of silicon dioxide, and the thickness of the buried oxide region is 400 nm or more.
15 . The semiconductor device according to claim 13 , wherein the buried oxide region is a SON (Silicon-ON-Nothing) layer, and the thickness of the buried oxide region is 150 nm or more.
16 . The semiconductor device according to claim 13 , wherein the thickness of the gate insulation film is thicker at the edge side of the gate electrode than at the center side of the gate electrode.
17 . A fabrication method for a semiconductor device comprising:
forming, via a gate insulation film, a gate electrode on the surface of a high resistivity semiconductor substrate a part of which is formed with a buried oxide film;
covering the surface of a gate electrode at a buried oxide region side and the surface of the high resistivity semiconductor substrate at the buried oxide region side with photo resist;
forming a first semiconductor region by implanting first conductive type ions into the surface layer of the high resistivity semiconductor substrate;
removing the photo resist from the high resistivity semiconductor substrate on which the first semiconductor region is formed;
forming a low resistivity drain region by implanting second conductive type ions into the surface layer of the high resistivity semiconductor substrate;
forming a spacer region on the side face of the gate electrode on the surface of the high resistivity semiconductor substrate on which the low resistivity region is formed; and
forming a second semiconductor region by implanting second conductive type ions into the surface layer of the high resistivity semiconductor substrate on which the spacer region is formed.
18 . A fabrication method for a semiconductor device comprising:
forming, via a gate insulation film, a pseudo-gate electrode on a surface of a high resistivity semiconductor substrate a part of which is formed with a buried oxide film;
covering a surface of the pseudo-gate electrode at a buried oxide region side and a surface of the high resistivity semiconductor substrate at the buried oxide region side with photo resist;
forming a first semiconductor region by implanting first conductive type ions into the surface layer of the high resistivity semiconductor substrate;
removing the photo resist from the high resistivity semiconductor substrate on which the first semiconductor region is formed;
forming a low resistivity drain region by implanting second conductive type ions into the surface layer of the high resistivity semiconductor substrate;
forming a spacer region on the side face of the pseudo-gate electrode on the surface of the high resistivity semiconductor substrate on which the low resistivity region is formed;
forming a second semiconductor region by implanting second conductive type ions into the surface layer of the high resistivity semiconductor substrate on which the spacer region is formed; and
forming a gate electrode after removing the pseudo-gate electrode.
19 . A fabrication method for a semiconductor device comprising:
forming a device structure on a high resistivity semiconductor substrate a part of which is formed with a buried oxide region formed of silicon dioxide; and
forming a SON layer by removing the silicon dioxide by etching.