PLL circuit for increasing potential difference between ground voltage and reference voltage or power source voltage of oscillation circuit

1. A PLL circuit comprising:

a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal;

an oscillation circuit, connected to the phase comparator, for outputting an oscillation signal having a frequency in accordance with the frequency control signal output from the phase comparator, a power source voltage, and a predetermined reference voltage; and

a bias control circuit, connected to the oscillation circuit, for increasing either the potential difference between the reference voltage of the oscillation circuit and a ground voltage or the potential difference between the power source voltage of the oscillation circuit and the ground voltage.

2. The PLL circuit in accordance with claim 1 , wherein:

the oscillation circuit includes:

a charge pump circuit into which the frequency control signal is input;

a loop filter into which a current in accordance with the frequency control signal and the power source voltage is input from the charge pump circuit, so as to output a control voltage; and

a voltage-controlled oscillator for outputting the oscillation signal having an oscillation frequency in accordance with the potential difference between the reference voltage and the control voltage output from the loop filter; and

the bias control circuit inputs the reference voltage into the voltage-controlled oscillator via a reference-voltage terminal thereof, where the input reference voltage is lower than the ground voltage.

3. The PLL circuit in accordance with claim 1 , wherein:

the oscillation circuit includes:

a charge pump circuit into which the frequency control signal is input;

a loop filter into which a current in accordance with the frequency control signal and the power source voltage is input from the charge pump circuit, so as to output a control voltage; and

a voltage-controlled oscillator for outputting the oscillation signal having an oscillation frequency in accordance with the potential difference between the reference voltage and the control voltage output from the loop filter; and

the bias control circuit inputs the power source voltage into the charge pump circuit via a power source voltage terminal thereof, where the input power source voltage is higher than an original power source voltage.

4. The PLL circuit in accordance with claim 2 , wherein:

the bias control circuit is a negative-voltage generating circuit for inputting a negative voltage as the reference voltage input into the reference-voltage terminal of the voltage-controlled oscillator.

5. The PLL circuit in accordance with claim 3 , wherein:

the bias control circuit is a booster circuit for inputting a voltage obtained by boosting the original power source voltage, into the power source voltage terminal of the charge pump circuit.

6. The PLL circuit in accordance with claim 2 , wherein:

the bias control circuit includes:

a negative-voltage generating circuit for generating a negative voltage; and

a first voltage control circuit for receiving the negative voltage via an input terminal thereof, changing the value of the negative voltage in accordance with a control signal input via a control terminal thereof, and inputting the changed negative voltage as the reference voltage into the reference-voltage terminal of the voltage-controlled oscillator.

7. The PLL circuit in accordance with claim 3 , wherein:

the bias control circuit includes:

a booster circuit for boosting the original power source voltage; and

a second voltage control circuit for receiving the boosted power source voltage via an input terminal thereof, changing the value of the power source voltage in accordance with a control signal input via a control terminal thereof, and inputting the changed power source voltage into the power source voltage terminal of the charge pump circuit.

8. The PLL circuit in accordance with claim 6 , wherein the first voltage control circuit includes:

a first NMOS transistor whose gate and drain are connected to the control terminal;

a second NMOS transistor whose gate and drain are connected to the source of the first NMOS transistor;

a third NMOS transistor whose gate and drain are connected to the source of the second NMOS transistor, and whose source is connected to an output terminal used for outputting a signal to the voltage-controlled oscillator;

a fourth NMOS transistor whose drain is connected to the output terminal, and whose source is connected to the negative-voltage generating circuit; and

an amplifier, one input terminal of which is connected to the source of the second NMOS transistor and the gate and drain of the third NMOS transistor, and the other input terminal of which is grounded, wherein the output terminal of the amplifier is connected to the gate of the fourth NMOS transistor.

9. The PLL circuit in accordance with claim 7 , wherein the second voltage control circuit includes:

a first PMOS transistor whose source is connected to the booster circuit, and whose drain is connected to an output terminal used for outputting a signal to the charge pump circuit; and

an amplifier, one input terminal of which is connected to the control terminal, and the other input terminal is connected to the output terminal, wherein the output terminal of the amplifier is connected to the gate of the first PMOS transistor.

10. The PLL circuit in accordance with claim 2 , wherein:

the voltage-controlled oscillator includes:

a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, whose sources are connected to an input terminal used for receiving the control voltage from the loop filter; and

a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, whose sources are connected to the reference-voltage terminal;

the drains of the first PMOS transistor and the first NMOS transistor are connected to the gates of the second PMOS transistor and the second NMOS transistor;

the drains of the second PMOS transistor and the second NMOS transistor are connected to the gates of the third PMOS transistor and the third NMOS transistor;

the drains of the third PMOS transistor and the third NMOS transistor are connected to an output terminal used for outputting the oscillation signal; and

the gates of the first PMOS transistor and the first NMOS transistor are connected to the output terminal.

11. The PLL circuit in accordance with claim 3 , wherein:

the frequency control signal is one of an increase signal for increasing the frequency of the oscillation signal and a decrease signal for decreasing the frequency of the oscillation signal;

the charge pump circuit includes:

a first PMOS transistor and a second PMOS transistor, whose sources are connected to the power source voltage terminal, and whose gates are connected to a bias voltage terminal into which a bias voltage is input;

a third PMOS transistor, whose source is connected to the drain of the second PMOS transistor, wherein the increase signal is input into the gate of the third PMOS transistor,

a first NMOS transistor, whose drain and gate are connected to the drain of the first PMOS transistor, wherein the source of the first NMOS transistor is grounded;

a second NMOS transistor in which the decrease is input into the gate thereof, and the drain of the second NMOS transistor is connected to the drain of the third PMOS transistor; and

a third NMOS transistor, whose source is grounded, and whose drain and gate are respectively connected to the source of the second NMOS transistor and the gate of the first NMOS transistor; and

the drains of the third PMOS transistor and the second NMOS transistor are connected to an output terminal used for outputting a signal to the loop filter.

12. A DRAM comprising:

a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal;

a charge pump circuit into which the frequency control signal is input;

a loop filter into which a current in accordance with the frequency control signal and the power source voltage is input from the charge pump circuit, so as to output a control voltage;

a voltage-controlled oscillator for outputting the oscillation signal having an oscillation frequency in accordance with the potential difference between the reference voltage and the control voltage output from the loop filter;

a negative-voltage generating part for generating a back bias voltage which is a negative voltage; and

a first voltage control circuit for receiving the back bias voltage via an input terminal thereof, changing the value of the back bias voltage in accordance with a control signal input via a control terminal thereof, and inputting the changed back bias voltage as the reference voltage into the voltage-controlled oscillator.

13. A DRAM comprising:

a phase comparator for outputting a frequency control signal based on a result of comparison between phases of an input reference clock signal and a fed-back oscillation signal;

a charge pump circuit into which the frequency control signal is input;

a loop filter into which a current in accordance with the frequency control signal and the power source voltage is input from the charge pump circuit, so as to output a control voltage;

a voltage-controlled oscillator for outputting the oscillation signal having an oscillation frequency in accordance with the potential difference between the reference voltage and the control voltage output from the loop filter;

a high-voltage generating part for outputting a word-line voltage higher than an original power source voltage; and

a second voltage control circuit for receiving the word-line voltage via an input terminal thereof, changing the value of the word-line voltage in accordance with a control signal input via a control terminal thereof, and inputting the changed word-line voltage into the charge pump circuit.