High density planar electrical interface
View Patent ↗An apparatus including a substrate having a plurality of through holes and a plurality of cables, including wires and/or coaxial cables, extending through respective ones of the plurality of through holes of the substrate. Each of the cables comprises a conductor and terminates about a surface of the substrate such that the conductors of respective ones of plurality of cables are planarly aligned and available for electrical contact. A system including a cable interface extending through respective ones of a plurality of through holes of a body of the interface; an interconnection component comprising a first plurality of contact points aligned with respective ones of conductors of the plurality of cables and a second plurality of contact points aligned to corresponding contact points of a device to be tested. Also, a method of routing signals through the conductors of the plurality of cables between electronic components.
1. A method comprising:
providing a plurality of cables in an array, the plurality of cables comprising respective conductors each having a first end and a second end, and having the first ends disposed in a plane of a body of the array, the first ends disposed at a pitch suitable for interfacing with one or more chip-scale components; and
forming a dielectric material in place around the first ends to hold the first ends, wherein the first ends are exposed on a surface of the dielectric material; and
introducing contact pads onto the respective first ends of the plurality of cables.
2. The method of claim 1 , wherein providing a plurality of cables in an array comprises:
providing a substrate comprising a plurality of holes spaced at the pitch suitable for interface with one more chip-scale components; and
inserting the first ends of the plurality of cables though the plurality of holes.
3. The method of claim 1 , wherein forming a dielectric material in place around the first ends comprises:
potting the plurality of cables in the dielectric material; and
planarizing a surface of the dielectric material to expose the first ends.
4. The method of claim 1 , wherein introducing contact pads over the respective conductors comprises coating the first ends with a conductive material.
5. The method of claim 1 , further comprising routing signals through the conductors of the plurality of cables between a first electronic component and a second electronic component.
6. The method of claim 5 , wherein the first electronic component is a testing component, the method further comprising:
coupling the conductors of the plurality of cables to an interconnection component comprising a plurality of contact points corresponding to contact points of the second electronic component.
7. The method of claim 6 , wherein coupling the conductors to an interconnection component further comprises modifying a contact pitch of the conductors to a contact pitch of the second electronic component.
8. The method of claim 5 , wherein the conductors of the plurality of cables comprise first conductors and routing signals comprises routing data signals, the method further comprising:
assembling second conductors designated as supply and return lines in a second different array; and
routing supply and return through the second conductors between the first electronic component and the second component.
9. The method of claim 4 , further comprising patterning the conductive material to form the contact pads.