Method and system for task switching with inline execution
The present disclosure is directed to a method and system for task switching with inline execution. In accordance with a particular embodiment of the present disclosure, a first state and a second state are identified for a function executing in the first state. A switch routine is invoked at a particular execution point in the function. A work element is generated in the switch routine. The work element includes status information for the function. The work element is transmitted to at least one alternate state task. The first state is altered to the second state according to the work element. Execution of the function in the second state is resumed at the particular execution point.
1. A method, comprising:
identifying a first state and a second state for a function, the function executing in the first state;
invoking a switch routine at a particular execution point in the function;
generating, in the switch routine, a work element, the work element comprising status information for the function;
transmitting the work element to at least one alternate state task;
altering the first state to the second state according to the work element; and
resuming execution of the function at the particular execution point in the second state.
2. The method of claim 1 , wherein altering the first state to the second state according to the work element comprises altering at least one general register value, at least one access register value, and at least one execution key.
3. The method of claim 1 , further comprising altering the second state to the first state by invoking a return routine.
4. The method of claim 1 , further comprising: storing at least one address reference operable to identify the particular execution point;
identifying an error; and
restoring the function at the particular execution point according to the at least one address reference.
5. The method of claim 1 , wherein the first state comprises a cross memory state and the second state comprises a non-cross memory state.
6. The method of claim 1 , wherein invoking a switch routine at a particular execution point in the function comprises invoking a macro.
7. The method of claim 1 , wherein the work element comprising status information for the function comprises at least one general register value, at least one access register value, and at least one execution key.
8. A system, comprising:
a processor; and
a storage device embodying a program of instructions operable, when executed on the processor, to:
identify a first state and a second state for a function, the function executing in the first state;
invoke a switch routine at a particular execution point in the function;
generate a work element, the work element comprising status information for the function;
transmit the work element to at least one alternate state task;
alter the first state to the second state according to the work element; and
resume execution of the function at the particular execution point in the second state.
9. The system of claim 8 , wherein the program of instructions is further operable to alter at least one general register value, at least one access register value, and at least one execution key.
10. The system of claim 8 , wherein the program of instructions is further operable to alter the second state to the first state by invoking a return routine.
11. The system of claim 8 , wherein the program of instructions is further operable to:
store at least one address reference operable to identify the particular execution point;
identify an error; and
restore the function at the particular execution point according to the at least one address reference.
12. The system of claim 8 , wherein the first state comprises a cross memory state and the second state comprises a non-cross memory state.
13. The system of claim 8 , wherein the program of instructions is further operable to invoke a macro.
14. The system of claim 8 , wherein the work element comprising status information for the function comprises at least one general register value, at least one access register value, and at least one execution key.
15. Logic encoded in non-transitory media, the logic being operable, when executed on a processor, to:
identify a first state and a second state for a function, the function executing in the first state;
invoke a switch routine at a particular execution point in the function;
generate a work element, the work element comprising status information for the function;
transmit the work element to at least one alternate state task;
alter the first state to the second state according to the work element; and
resume execution of the function at the particular execution point in the second state.
16. The logic of claim 15 , wherein the logic is further operable to alter at least one general register value, at least one access register value, and at least one execution key.
17. The logic of claim 15 , wherein the logic is further operable to alter the second state to the first state by invoking a return routine.
18. The logic of claim 15 , wherein the logic is further operable to:
store at least one address reference operable to identify the particular execution point;
identify an error; and
restore the function at the particular execution point according to the at least one address reference.
19. The logic of claim 15 , wherein the first state comprises a cross memory state and the second state comprises a non-cross memory state.
20. The logic of claim 15 , wherein the work element comprising status information for the function comprises at least one general register value, at least one access register value, and at least one execution key.