IP Library Granted Patent US 7,642,945
Granted Patent B2
US 7,642,945 · App. 12/035,899 · Granted Jan 5, 2010

AD converter circuit and microcontroller

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Quick Facts
Patent No.
US 7,642,945
App. No.
12/035,899
Granted
Jan 5, 2010
Kind
B2
Abstract

A successive approximation type AD converter circuit for comparing an analog input signal with an output analog signal of a DA converter with a comparator to input a digital signal output in accordance with a comparison result to the DA converter to determine a digital signal obtained if the output analog signal of the DA converter is equal to the analog input signal, as an AD-converted output signal, includes: an AD converter for AD-converting the analog input circuit in accordance with a sampling period for sampling the analog input signal and a comparison period for comparing the sampled analog input signal with the output analog signal of the DA converter with the comparator; and setting means for independently setting a cycle time of a first clock signal for determining the sampling period and a cycle time of a second clock signal for determining the comparison period.

Claims (55)

1. An AD converter circuit that is a successive approximation type, comprising:

a comparator for comparing an analog input signal with an output analog signal;

a DA converter for outputting the output analog signal according to a digital signal output in accordance with a comparison result from the comparator;

an AD converter for AD-converting the analog input signal to the digital signal output in accordance with a sampling period for sampling the analog input signal and comparison period for comparing the sampled analog input signal with the output analog signal of the DA converter, and for outputting an AD-converted output signal if the output analog signal of the DA converter is equal to the analog input signal; and

setting means for independently setting a cycle time of a first clock signal for determining the sampling period and a cycle time of a second clock signal for determining the comparison period, wherein the setting means comprises:

a first divider circuit for dividing a clock signal to generate the first clock signal;

a second divider circuit for dividing the clock signal to generate the second clock signal and supply the generated clock signal to the AD converter; and

a counter circuit for counting the number of the first clock signals to supply a control signal for setting the sampling period to the AD converter.

2. The AD converter circuit according to claim 1 , further comprising:

first and second registers in which a division ratio of the first divider circuit and a division ratio of the second divider circuit are separately set,

the division ratios being supplied to the first and second divider circuits from the first and second registers.

3. The AD converter circuit according to claim 2 , wherein a value of the first register and a value of the second register can be set by use of software.

4. The AD converter circuit according to claim 1 , further comprising:

a third register in which a count value of the counter circuit is set, the count value being supplied to the counter circuit from the third register.

5. A microcontroller having the AD converter circuit according to claim 4 , comprising:

a CPU; and

a clock generating circuit for generating the clock;

an AD converter circuit that is a successive approximation type, wherein the AD converter comprises:

a comparator for comparing an analog input signal with an output analog signal;

a DA converter for outputting the output analog signal according to a digital signal output in accordance with a comparison result from the comparator;

an AD converter for AD-converting the analog input signal to the digital signal output in accordance with a sampling period for sampling the analog input signal and comparison period for comparing the sampled analog input signal with the output analog signal of the DA converter, and for outputting an AD-converted output signal if the output analog signal of the DA converter is equal to the analog input signal;

setting means for independently setting a cycle time of a first clock signal for determining the sampling period and a cycle time of a second clock signal for determining the comparison period;

a third register in which a count value of the counter circuit is set,

the count value being supplied to the counter circuit from the third register,

wherein the setting means comprises:

a first divider circuit for dividing a clock signal to generate the first clock signal;

a second divider circuit for dividing the clock signal to generate the second clock signal and supply the generated clock signal to the AD converter; and

a counter circuit for counting the number of the first clock signals to supply a control signal for setting the sampling period to the AD converter.

6. The microcontroller according to claim 5 , wherein the CPU sets a value of the first register and a value of the second register by way of software.

7. The AD converter circuit according to claim 4 , wherein a value of the third register can be set by use of software.

8. The AD converter circuit according to claim 1 , further comprising:

a fourth register in which a current value of a current in the comparator is set, the current value being supplied to the AD converter from the fourth register.

9. The AD converter circuit according to claim 8 , wherein a value of the fourth register can be set by use of software.

10. The type AD converter circuit according to claim 1 , wherein the DA converter is one converter selected from the group consisting of a capacitor DA converter, a resistor DA converter, and a DA converter that combines a capacitor DA converter and a resistor DA converter.

11. The AD converter circuit according to claim 1 , wherein the comparator comprises a plurality of differential amplifier circuits, and the AD converter comprises a reference voltage generating circuit for applying a comparison reference potential to a positive input terminal of each of the differential amplifier circuits and a fifth register in which a current value of a current of a resistance-divided circuit for generating the comparison reference potential.

12. The AD converter circuit according to claim 11 , wherein a value of the fifth register can be set by use of software.

13. The AD converter circuit according to claim 1 , wherein the comparator comprises a plurality of single-ended amplifier circuits, and the AD converter comprises a current mirror circuit for determining a current value of a current of each of the signal-ended amplifier circuits.

14. A microcontroller having the AD converter circuit according to claim 1 , comprising:

a CPU; and

a clock generating circuit for generating the clock.

15. A microcontroller, comprising:

a CPU;

a clock generating circuit for generating the clock; and

an AD converter circuit that is a successive approximation type, wherein the AD converter comprises:

a comparator for comparing an analog input signal with an output analog signal;

a DA converter for outputting the output analog signal according to a digital signal output in accordance with a comparison result from the comparator;

an AD converter for AD-converting the analog input signal to the digital signal output in accordance with a sampling period for sampling the analog input signal and comparison period for comparing the sampled analog input signal with the output analog signal of the DA converter, and for outputting an AD-converted output signal if the output analog signal of the DA converter is equal to the analog input signal;

setting means for independently setting a cycle time of a first clock signal for determining the sampling period and a cycle time of a second clock signal for determining the comparison period;

first and second registers in which a division ratio of the first divider circuit and a division ratio of the second divider circuit are separately set; and

the division ratios being supplied to the first and second divider circuits from the first and second registers,

wherein the selling means comprises:

a first divider circuit for dividing a clock signal to generate the first clock signal;

a second divider circuit for dividing the clock signal to generate the second clock signal and supply the generated clock signal to the AD converter; and

a counter circuit for counting the number of the first clock signals to supply a control signal for setting the sampling period to the AD converter.

16. The microcontroller according to claim 15 , wherein the CPU sets a value of the first register and a value of the second register by way of software.

Assignments (10)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036049/0581 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024982/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021977/0219 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2008
From: TACHIBANA, SUGURU; HIRAISHI, IKUO; SAITO, AZUSA
To: FUJITSU LIMITED
Reel/Frame 020565/0262 →