Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1 . A semiconductor chip comprising:
a silicon substrate;
multiple transistors on said silicon substrate;
a first metal layer over said silicon substrate;
a second metal layer over said silicon substrate;
a dielectric layer between said first and second metal layers;
a first metal interconnect over said silicon substrate;
a second metal interconnect over said silicon substrate;
a third metal interconnect over said silicon substrate and between said first and second metal interconnects;
a fourth metal interconnect over said silicon substrate and between said third and second metal interconnects, wherein said first, second, third and fourth metal interconnects are separated from one another by an insulating material;
a passivation layer over said first and second metal layers, over said dielectric layer and on said third and fourth metal interconnects, wherein said first, second, third and fourth metal interconnects are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost oxide layer of said semiconductor chip;
a polymer layer on said passivation layer and over said third and fourth metal interconnects, wherein said polymer layer has a thickness between 2 and 30 micrometers, greater than that of said passivation layer and greater than that of said dielectric layer, and wherein a first opening in said passivation layer and in said polymer layer is over a first contact point of said first metal interconnect and exposes said first contact point, and a second opening in said passivation layer and in said polymer layer is over a second contact point of said second metal interconnect and exposes said second contact point; and
an interconnecting structure on said polymer layer, over said passivation layer, over said third and fourth metal interconnects and over said first and second contact points, wherein said third and fourth metal interconnects are directly under said interconnecting structure and are not connected to said interconnecting structure through any opening in said polymer layer under said interconnecting structure, wherein said first contact point is connected to said second contact point through said interconnecting structure, wherein said interconnecting structure comprises electroplated copper in said first and second openings and over said polymer layer, and wherein said interconnecting structure comprises a third metal layer, on said polymer layer, having a thickness greater than that of said first metal layer and greater than that of said second metal layer.
2 . The semiconductor chip of claim 1 , wherein said polymer layer comprises polyimide.
3 . The semiconductor chip of claim 1 , wherein said polymer layer comprises benzocyclobutene (BCB).
4 . The semiconductor chip of claim 1 , wherein said topmost metal layer under said passivation layer comprises electroplated copper.
5 . The semiconductor chip claim 1 , wherein said topmost metal layer under said passivation layer comprises aluminum.
6 . The semiconductor chip of claim 1 , wherein said topmost nitride layer is over said topmost oxide layer.
7 . The semiconductor chip of claim 1 , wherein said interconnecting structure comprises a power interconnect connecting said first contact point to said second contact point.
8 . A semiconductor chip comprising:
a silicon substrate;
multiple transistors on said silicon substrate;
a first metal layer over said silicon substrate;
a second metal layer over said silicon substrate;
a dielectric layer between said first and second metal layers;
a first metal interconnect over said silicon substrate;
a second metal interconnect over said silicon substrate;
a third metal interconnect over said silicon substrate and between said first and second metal interconnects, wherein said first, second and third metal interconnects are separated from one another by an insulating material;
a passivation layer over said first and second metal layers, over said dielectric layer and on said third metal interconnect, wherein said first, second and third metal interconnects are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost oxide layer of said semiconductor chip;
a polymer layer on said passivation layer and over said third metal interconnect, wherein said polymer layer has a thickness between 2 and 30 micrometers, greater than that of said passivation layer and greater than that of said dielectric layer, and wherein a first opening in said passivation layer and in said polymer layer is over a first contact point of said first metal interconnect and exposes said first contact point, and a second opening in said passivation layer and in said polymer layer is over a second contact point of said second metal inter connect and exposes said second contact point; and
an interconnecting structure on said polymer layer, over said passivation layer, over said third metal interconnect and over said first and second contact points, wherein said third metal interconnect is directly under said inter connecting structure and is not connected to said interconnecting structure through any opening in said polymer layer under said interconnecting structure, wherein said first contact point is connected to said second contact point through said interconnecting structure, wherein said interconnecting structure comprises electroplated copper in said first and second openings and over said polymer layer, and wherein said interconnecting structure comprises a third metal layer, on said polymer layer, having a thickness greater than that of said first metal layer and greater than that of said second metal layer.
9 . The semiconductor chip of claim 8 , wherein said polymer layer comprises polyimide.
10 . The semiconductor chip of claim 8 , wherein said polymer layer comprises benzocyclobutene (BCB).
11 . The semiconductor chip of claim 8 , wherein said topmost metal layer under said passivation layer comprises electroplated copper.
12 . The semiconductor chip of claim 8 , wherein said topmost metal layer under said passivation layer comprises aluminum.
13 . The semiconductor chip of claim 8 , wherein said topmost nitride layer is over said topmost oxide layer.
14 . The semiconductor chip of claim 8 , wherein said interconnecting structure comprises a power interconnect connecting said first contact point to said second contact point.
15 . A semiconductor chip comprising:
a silicon substrate;
multiple transistors on said silicon substrate;
a first metal layer over said silicon substrate;
a second metal layer over said silicon substrate;
a dielectric layer between said first and second metal layers;
a first metal interconnect over said silicon substrate;
a second metal interconnect over said silicon substrate;
a third metal interconnect over said silicon substrate and between said first and second metal interconnects, wherein said first, second and third metal interconnects are separated from one another by an insulating material;
a passivation layer over said first and second metal layer's and over said dielectric layer, wherein said first, second and third metal inter connects are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost oxide layer of said semiconductor chip;
a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 30 micrometers, greater than that of said passivation layer and greater than that of said dielectric layer, and wherein a first opening in said passivation layer and in said polymer layer is over a first contact point of said first metal interconnect and exposes said first contact point, and a second opening in said passivation layer and in said polymer layer is over a second contact point of said second metal interconnect and exposes said second contact point; and
an interconnecting structure on said polymer layer, over said passivation layer, over said third metal interconnect and over said first and second contact points, wherein said third metal interconnect is directly under said interconnecting structure and is not connected to said inter connecting structure through any opening in said polymer layer under said inter connecting structure, wherein said first contact point is connected to said second contact point through said interconnecting structure, wherein said interconnecting structure comprises electroplated copper in said first and second openings and over said polymer layer, and wherein said interconnecting structure comprises a third metal layer, on said polymer layer, having a thickness greater than that of said first metal layer and greater than that of said second metal layer.
16 . The semiconductor chip of claim 15 , wherein said polymer layer comprises polyimide.
17 . The semiconductor chip of claim 15 , wherein said polymer layer comprises benzocyclobutene (BCB).
18 . The semiconductor chip of claim 15 , wherein said topmost metal layer under said passivation layer comprises electroplated copper.
19 . The semiconductor chip of claim 15 , wherein said topmost metal layer under said passivation layer comprises aluminum.
20 . The semiconductor chip of claim 15 , wherein said interconnecting structure comprises a power interconnect connecting said first contact point to said second contact point.