Computer system and memory system
View Patent ↗A computer system includes a CPU, a memory circuit storing at least instruction codes, an error checking circuit checking an error of an instruction code read from the memory circuit according to an instruction address supplied from the CPU, a code storing circuit storing data to be outputted to the CPU instead of data from the memory when an error occurs, a selection circuit in which inputs are coupled to the memory circuit and the code storing circuit, and selectively outputting data from the code storing circuit when an error is detected by the error checking circuit, a bus connecting the selection circuit to the CPU, and an instruction error register storing a value indicating that an error occurs when the error is detected by the error checking circuit.
1. A computer system, comprising:
a CPU;
a memory circuit storing at least instruction codes;
an error checking circuit checking an error of an instruction code read from the memory circuit according to an instruction address supplied from the CPU;
a code storing circuit storing data, which makes the CPU execute an exception handling, to be outputted to the CPU instead of data from the memory when an error occurs;
a selection circuit in which inputs are coupled to the memory circuit and the code storing circuit, selectively outputting an instruction code read from the memory circuit when an error is not detected by the error checking circuit, and selectively outputting data from the code storing circuit to execute the exception handling when an error is detected by the error checking circuit;
a bus connecting the selection circuit to the CPU; and
an instruction error register storing a value indicating that an error occurs when the error is detected by the error checking circuit, and
wherein the CPU is configured to output a signal indicating that an instruction is not executed when the instruction fetched through the bus is not executed, to execute the exception handling when the instruction fetched through the bus is the data and the signal indicating that the instruction is not executed is not output and not to decode the instruction in a decode cycle based on the signal when the instruction fetched through the bus is the data and the signal indicating that the instruction is not executed is output, and
the instruction error register is set to a state of storing a value indicating that an error does not occur in response to the signal indicating that the instruction is not executed.
2. The computer system according to claim 1 , wherein the code storing circuit stores a code which causes an undefined instruction exception.
3. The computer system according to claim 1 , wherein the signal is supplied to a reset terminal of the instruction error register from the CPU through a signal line.
4. The computer system according to claim 1 , wherein a previous instruction which is fetched prior to the instruction by the CPU is a JUMP instruction and a decoded JUMP instruction is determined to jump.
5. The computer system according to claim 1 , wherein the CPU does not execute the exception handling when the instruction fetched through the bus is the data and the signal indicating that the instruction is not executed is output.
6. The computer system according to claim 1 , wherein the CPU outputs a vector address in the exception handling and fetches a start address of an exception hander from vector addresses of the memory circuit.
7. The computer system according to claim 6 , wherein the CPU outputs a type specification signal indicating which of the instruction address and the vector address is outputted.
8. The computer system according to claim 7 , further comprising:
a vector error register, and
wherein the instruction error register is configured to store a value indicating that an error occurs in the case that the error is detected by the error checking circuit as well as the type specification signal indicates an instruction address output, and the vector error register is configured to store a value indicating that an error occurs in the case that the error is detected by the error checking circuit as well as the type specification signal indicates a vector address output.
9. A memory system, comprising:
a memory circuit storing instruction codes;
an error checking circuit checking an error of an instruction code read from the memory circuit according to an instruction address supplied from an external bus;
a code storing circuit storing data, which makes the CPU execute an exception handling, to be outputted to a CPU instead of data from the memory when an error occurs;
a selection circuit in which inputs are coupled to the memory circuit and the code storing circuit, selectively outputting an instruction code read from the memory circuit to the external bus when an error is not detected by the error checking circuit, and selectively outputting data to execute the exception handling from the code storing circuit to the external bus when an error is detected by the error checking circuit; and
an instruction error register storing a value indicating that an error occurs when the error is detected by the error checking circuit and is reset to a state of storing a value indicating that an error does not occur in response to a signal indicating that an instruction is not executed which is input from the external bus to a terminal connected to the external bus,
wherein the exception handling is executed when the instruction fetched through the bus is the data and the signal indicating that the instruction is not executed is not output and the instruction is not decoded in a decode cycle based on the signal when the instruction fetched through the bus is the data and the signal indicating that the instruction is not executed is output.
10. The memory system according to claim 9 , further comprising:
a vector storing circuit storing start addresses of exception handlers performing a process to be executed when an undefined instruction occurs, and wherein the selection circuit in which inputs are coupled to the memory circuit, the code storing circuit and the vector storing circuit, selectively outputting the data from the code storing circuit to the external bus when an error is detected by the error checking circuit as well as a type specification signal from the external bus indicates an instruction address supply, and selectively outputting a start address of the exception handler from the vector storing circuit to the external bus when an error is detected by the error checking circuit as well as the type specification signal from the external bus indicates a vector address supply.
11. A computer method, comprising:
storing a plurality of instruction codes in a memory circuit;
reading one of the instruction codes from the memory circuit according to an instruction address supplied from a CPU;
checking the instruction code for an error;
storing substitute data, which makes the CPU execute an exception handling, to be outputted to the CPU instead of data from the memory when an error occurs;
selectively outputting an instruction code read from the memory circuit if an error is not detected;
selectively outputting the substitute data to execute the exception handling if an error is detected;
storing a value indicating that an error occurred if the error is detected, and
outputting a signal indicating that an instruction was not executed when the instruction was not executed;
executing the exception handling when the instruction fetched through the bus is the data and the signal indicating that the instruction is not executed is not output;
not decoding the instruction in a decode cycle based on the signal when the instruction fetched through the bus is the data and the signal indicating that the instruction is not executed is output; and
storing a value indicating that an error did not occur in an instruction error register in response to the signal indicating that the instruction was not executed.