IP Library Granted Patent US 7,706,599
Granted Patent B2
US 7,706,599 · App. 12/036,679 · Granted Apr 27, 2010

Edge normal process

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,706,599
App. No.
12/036,679
Granted
Apr 27, 2010
Kind
B2
Abstract

An edge inspection method for detecting defects on a wafer edge normal surface includes acquiring a set of digital images which captures a circumference of the wafer. An edge of the wafer about the circumference is determined. Each digital image is segmented into a plurality of horizontal bands. Adjacent edge clusters about the circumference of the wafer are combined into edge pixel bins. The edge pixel bins are analyzed via edge clusters analysis to identify defects. The edge pixel bins are also analyzed via blob analysis to determine defects.

Claims (32)

1. A method of inspecting an edge of a semiconductor wafer comprising:

capturing an image of a wafer edge from generally above a plane of the wafer;

identifying a location of the wafer edge from the previously captured image;

focusing an imaging device positioned generally radially outwardly from the edge of the wafer;

illuminating at least a portion of an edge normal surface of the edge of the wafer using at least one of brightfield and darkfield illumination;

capturing at least one image of the at least a portion of the edge normal surface of the edge of the wafer; and

processing the at least one image with a controller to identify a defect on the edge of the wafer, if any.

2. The method of inspecting an edge of a semiconductor wafer of claim 1 , wherein capturing at least one image of the at least a portion of an edge normal surface of the edge of the wafer further comprises:

capturing simultaneously at least a portion of a top bevel of the wafer edge and a bottom bevel of the wafer edge.

3. The method of inspecting an edge of a semiconductor wafer of claim 2 , further comprising:

calculating a thickness of a wafer by determining at least a first thickness of the wafer and a second thickness of the wafer at spaced apart locations and averaging the at least first and second thicknesses to identify an average thickness of the wafer.

4. The method of inspecting an edge of a semiconductor wafer of claim 1 , further comprising:

identifying an upper surface of the wafer and a lower surface of the wafer and calculating a thickness of the wafer.

5. The method of inspecting an edge of a semiconductor wafer of claim 1 , wherein capturing at least one image of the at least a portion of an edge normal surface of the edge of the wafer further comprises:

illuminating the at least a portion of an edge normal surface of the edge of the wafer using both brightfield and darkfield illumination.

6. A process of producing a semiconductor device comprising:

forming, at least partially, at least one semiconductor device on a wafer;

inspecting at least a portion of an edge of the wafer by:

capturing at least one image of an edge of the wafer,

processing the at least one image of the edge of the wafer with a controller to identify defects in the image, wherein processing includes comparing the at least one image to a reference image to produce a difference image, and

exporting data concerning at least one of the found defects;

wherein the at least one image includes image data from at least one distinct portion of the edge of a wafer, the at least one distinct portion of the edge chosen from a group consisting of an edge exclusion region, a top bevel region, an edge normal region, a bottom bevel region, and a bottom surface region; and

modifying at least one semiconductor manufacturing process used to at least partially form the least one semiconductor device on a wafer on the basis of the exported data.

7. A product provided by the process of claim 6 .

8. A method of inspecting a semiconductor wafer comprising:

capturing at least one image of an edge of a wafer;

processing the at least one image of the edge of the wafer with a controller to identify at least one wafer top location and at least one wafer bottom location within the at least one image;

calculating a wafer thickness value from the at least one wafer top and at least one wafer bottom locations by determining at least a first thickness of the wafer and a second thickness of the wafer at spaced apart locations and averaging the at least first and second thicknesses to identify an average thickness of the wafer; and

exporting data concerning the wafer thickness value for each image.

9. The method of inspecting a semiconductor wafer of claim 8 , further comprising:

identify defects in the at least one image by comparing the at least one image to a reference image to produce a difference image; and

exporting data concerning at least one found defect, if any.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE TITLE AND ADD INVENTOR'S HAK CHUAH SIM AND AUGUST TECHNOLOGY CORP. PREVIOUSLY RECORDED AT REEL: 053117 FRAME: 0623. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 5, 2021
From: SIM, HAK CHUAH; AUGUST TECHNOLOGY CORP.; RUDOLPH TECHNOLOGIES, INC.
To: ONTO INNOVATION INC.
Reel/Frame 057746/0800 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2020
From: RUDOLPH TECHNOLOGIES, INC.
To: ONTO INNOVATION INC.
Reel/Frame 053117/0623 →