Method for forming a nickelsilicide FUSI gate
View Patent ↗Ni 3 Si 2 FUSI gates can be formed inter alia by further reaction of NiSi/Ni 2 Si gate stacks. Ni 3 Si 2 behaves similarly to NiSi in terms of work function values, and of modulation with dopants on SiO 2 , in contrast to Ni-rich silicides which have significantly higher work function values on HfSi x O y and negligible work function shifts with dopants on SiO 2 . Formation of Ni 3 Si 2 can applied for applications targeting NiSi FUSI gates, thereby expanding the process window without changing the electrical properties of the FUSI gate.
1. A method of fabricating a nickel fully-silicided-gate electrode device, the method comprising:
providing a metal-oxide-semiconductor field-effect transistor (MOSFET) device having a semiconductor gate electrode formed on a gate dielectric;
providing a nickel layer in contact with the semiconductor gate electrode;
performing a silicidation process to form a Ni 3 Si 2 silicide at least at an interface between the semiconductor gate electrode with the gate dielectric; and
incorporating a dopant in the Ni 3 Si 2 silicide to modulate a work function thereof.
2. The method of claim 1 , wherein the dopant is selected from the group consisting of phosphorous and boron.
3. A method of fabricating a nickel fully-silicided-gate electrode device, the method comprising:
providing a metal-oxide-semiconductor field-effect transistor (MOSFET) device having a semiconductor gate electrode formed on a gate dielectric;
providing a nickel layer in contact with the semiconductor gate electrode; and
performing a silicidation process to form a Ni 3 Si 2 silicide at least at an interface between the semiconductor gate electrode with the gate dielectric, wherein the silicidation process comprises:
performing a first thermal process step to react the semiconductor gate electrode with the provided nickel to form a gate electrode stack comprising NiSi and a metal-rich silicide phase;
selectively removing unreacted nickel; and
performing a second thermal process step to convert the gate electrode stack comprising NiSi and a metal-rich silicide phase into a Ni 3 Si 2 silicide phase.
4. The method of claim 3 , wherein the metal-rich silicide phase is Ni 2 Si.
5. The method of claim 3 , further comprising incorporating a dopant in the Ni 3 Si 2 silicide to modulate a work function thereof.
6. The method of claim 5 , wherein the dopant is selected from the group consisting of phosphorous and boron.
7. The method of claim 1 , wherein the gate dielectric is a silicon-oxide.
8. The method of claim 1 , wherein the gate dielectric is a hafnium-based high-k dielectric.
9. The method of claim 3 , wherein the gate dielectric is a silicon-oxide.
10. The method of claim 3 , wherein the gate dielectric is a hafnium-based high-k dielectric.
11. A method of fabricating a metal-oxide semiconductor (MOS) device, the method comprising:
providing a gate stack formed on a substrate, wherein the gate stack comprises a gate dielectric in contact with the substrate and a silicon gate electrode in contact with the gate dielectric;
depositing a nickel layer on the silicon gate electrode;
in a first thermal process step, thermally treating the gate electrode stack such that the nickel layer and the silicon gate electrode react to form a stack comprising NiSi and a metal-rich silicide phase;
after the first thermal process step, selectively removing unreacted nickel;
in a second thermal process step, after the selective removal of unreacted nickel, thermally treating the gate electrode stack such that the NiSi and the metal-rich silicide phase are converted into a Ni 3 Si 2 silicide phase at least at an interface between the gate electrode and the gate dielectric.
12. The method of claim 11 , wherein the metal-rich silicide phase comprises Ni 2 Si.
13. The method of claim 11 , wherein the first thermal process step has a first thermal budget of between about 360° C. and 30 seconds and about 380° C. and 30 seconds.
14. The method of claim 11 , wherein the second thermal process step has a second thermal budget of above about 500° C. and 30 seconds.
15. The method of claim 12 , wherein:
the first thermal process step has a first thermal budget of between about 360° C. and 30 seconds and about 380° C. and 30 seconds; and
the second thermal process step has a second thermal budget of above about 500° C. and 30 seconds.
16. The method of claim 11 , further comprising doping the gate electrode to modulate a work function thereof.
17. A metal-oxide-semiconductor field-effect transistor (MOSFET) comprising a gate electrode and a gate dielectric, wherein the gate electrode comprises Ni 3 Si 2 at least at an interface with the gate dielectric.
18. The MOSFET of claim 17 , wherein the Ni 3 Si 2 further comprises a dopant for modulating the work function thereof.
19. The MOSFET of claim 18 , wherein the dopant is selected from the group consisting of phosphorous and boron.