Magnetic random access memory and manufacturing method thereof

1. A magnetic random access memory comprising:

a semiconductor substrate in which a step portion having a side surface and a top face is formed;

a gate electrode formed on the side surface of the step portion through a gate insulating film;

a drain diffusion layer formed in the top face of the step portion;

a source diffusion layer formed in the semiconductor substrate below the drain diffusion layer to be separated from the drain diffusion layer;

a magnetoresistive effect element which is connected with the drain diffusion layer, and has a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, the magnetization directions of the fixed layer and the recording layer entering a parallel state or an antiparallel state in accordance with a direction of a current flowing through a space between the fixed layer and the recording layer; and

a bit line connected with the magnetoresistive effect element.

2. The memory according to claim 1 ,

wherein the step portion is a convex portion protruding from a substrate surface, and

the source diffusion layer is formed in the semiconductor substrate at the base of the convex portion.

3. The memory according to claim 2 ,

wherein the source diffusion layer has a space provided below the drain diffusion layer.

4. The memory according to claim 2 ,

wherein a planar shape of the gate electrode is a ring-like shape surrounding the side surface of the convex portion.

5. The memory according to claim 2 ,

wherein the magnetoresistive effect element is placed immediately above the convex portion.

6. The memory according to claim 2 , further comprising:

a contact which is formed on the convex portion, connected with the drain diffusion layer and the magnetoresistive effect element, and has the same planar shape as a planar shape of the convex portion.

7. The memory according to claim 2 , further comprising:

a word line which is formed on the semiconductor substrate and connected with the gate electrode,

wherein the source diffusion layer and the bit line are extended in the same first direction, and

the word line is extended in a second direction crossing the first direction.

8. The memory according to claim 2 , further comprising:

a word line which is formed on the semiconductor substrate and connected with the gate electrode,

wherein the source diffusion layer and the word line are extended in the same first direction, and

the bit line is extended in a second direction crossing the first direction.

9. The memory according to claim 2 ,

wherein the source diffusion layer and the bit line are extended in the same first direction, and

the gate electrode is extended in a second direction crossing the first direction.

10. The memory according to claim 9 ,

wherein the gate electrode is directly in contact with a gate electrode which is adjacent thereto in the second direction.

11. The memory according to claim 1 , further comprising:

a contact which is connected with the recording layer and has a contact area with respect to the recording layer being smaller than an area of the recording layer.

12. The memory according to claim 11 , further comprising:

a cap layer which is provided between the recording layer and the contact and has a resistance value higher than a resistance value of the recording layer.

13. The memory according to claim 1 ,

wherein the step portion is a concave portion which is depressed with respect to the substrate surface, and

the memory further comprises a source line which is formed on a bottom of the concave portion and connected with the source diffusion layer.