IP Library Granted Patent US 9,508,651
Granted Patent B2
US 9,508,651 · App. 12/039,511 · Granted Nov 29, 2016

Semiconductor device and method of manufacturing the same

Inventors: Masanori Onodera (Tokyo, JP); Junichi Kasai (Kanagawa, JP)
Assignee: Cypress Semiconductor Corporation
H01L23/5388H01L21/6835H01L23/49838H01L24/19H01L24/97H01L21/568H01L2221/68345H01L2224/02333H01L2224/04105H01L2224/20H01L2224/32225H01L2224/73267H01L2224/92244H01L2224/97H01L2924/01005H01L2924/01006H01L2924/01029H01L2924/01033H01L2924/01075H01L2924/01078H01L2924/01079H01L2924/14H01L2924/15311H01L2924/15787H01L2924/18162
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Quick Facts
Patent No.
US 9,508,651
App. No.
12/039,511
Granted
Nov 29, 2016
Kind
B2
Abstract

A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer.

Claims (36)

1. A semiconductor device comprising:

a semiconductor chip;

a bump electrode, at least partially spheroidal in shape, having a height of approximately 300 micrometers, formed on an upper face of the semiconductor chip wherein the bump electrode physically contacts the upper face of the semiconductor chip, wherein an upper face of the bump electrode is flat and wherein a lower face of the bump electrode that physically contacts the upper surface of the semiconductor chip is flat;

a molding portion that seals an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed;

a planar redistribution layer formed on an upper face of the molding portion and connected to the exposed part of the bump electrode, electrically coupled to the semiconductor chip via the bump electrode, wherein the height of the bump electrode is measured from the planar redistribution layer to the upper face of the semiconductor chip; and

a spheroidal outer connection electrode formed on an upper face of the redistribution layer that extends laterally beyond the redistribution layer, wherein the spheroidal outer connection electrode is electrically coupled to the bump electrode via the redistribution layer, wherein the spheroidal outer connection electrode is one of a plurality of outer connection electrodes that each lie laterally beyond sides of the semiconductor chip and wherein the bump electrode and the spheroidal outer connection electrode are positioned on opposite sides of the redistribution layer, wherein the redistribution layer is positioned directly underneath and connected to the spheroidal outer connection electrode.

2. The semiconductor device as claimed in claim 1 , wherein the upper face of the molding portion is flat.

3. The semiconductor device as claimed in claim 1 , wherein an interval between the spheroidal outer connection electrodes is larger than that between bump electrodes.

4. The semiconductor device as claimed in claim 1 , further comprising a substrate that is fixed to a lower face of the semiconductor chip.

5. The semiconductor device as claimed in claim 4 , wherein the substrate is a silicon substrate.

6. The semiconductor device as claimed in claim 1 , further comprising an insulating portion,

wherein:

the insulating portion covers an entire side face and a portion of the upper face of the redistribution layer; and

a part of the spheroidal outer connection electrode is exposed.

7. The semiconductor device as claimed in claim 1 , wherein the spheroidal outer connection electrode is located radially outside of the bump electrode as measured from a center of the semiconductor chip.

8. The semiconductor device as claimed in claim 1 , further comprising forming a fixing portion from epoxy resin that is coextensive with and fixed to a lower face of the semiconductor chip, wherein the fixing portion is encapsulated by the molding portion at both sides and a substrate at a bottom of the fixing portion.

9. The semiconductor device as claimed in claim 1 , wherein the bump electrode is one of a plurality of bump electrodes.

10. The semiconductor device as claimed in claim 1 , wherein the outer electrode is one of a plurality of spheroidal outer electrodes.

11. A method of manufacturing a semiconductor device comprising:

forming a bump electrode, at least partially spheroidal in shape, having a height of approximately 300 micrometers, on an upper face of a semiconductor chip, wherein the bump electrode physically contacts the upper face of the semiconductor chip, wherein an upper face of the bump electrode is flat and wherein a lower face of the bump electrode that physically contacts the upper surface of the semiconductor chip is flat;

fixing the semiconductor chip to an upper face of a substrate;

forming a molding portion that seals an entire face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed;

forming a planar redistribution layer on an upper face of the molding portion and connected to the exposed part of the bump electrode so that the redistribution layer is electrically coupled to the bump electrode, wherein the height of the bump electrode is measured from the planar redistribution layer to the upper face of the semiconductor chip; and

forming a spheroidal outer connection electrode, on an upper face of the redistribution layer that extends laterally beyond the redistribution layer so that the spheroidal outer connection electrode is electrically coupled to the bump electrode via the redistribution layer, wherein the spheroidal outer connection electrode is one of a plurality of outer connection electrodes that each lie laterally beyond sides of the semiconductor chip and wherein the bump electrode and the spheroidal outer connection electrode are positioned on opposite sides of the redistribution layer, wherein the redistribution layer is positioned directly underneath and connected to the spheroidal outer connection electrode.

12. The method of claim 11 , wherein the substrate is a silicon substrate.

13. The method of claim 11 , wherein to form the molding portion the method comprises:

arranging the substrate in a mold having a recess; and

forming the molding portion so as to seal the semiconductor chip.

14. The method of claim 11 , wherein to form the molding portion the method comprises fabricating the upper face of the molding portion and the upper face of the bump electrode to be flat.

15. The method of claim 11 , further comprising removing the substrate after forming the spheroidal outer connection electrode.

16. The method of claim 15 , wherein to remove the substrate the method comprises reducing a thickness of the semiconductor chip and a thickness of the molding portion.

17. The method of claim 11 , further comprising forming an insulating portion after forming the redistribution layer,

wherein the insulating portion is formed so that the insulating portion covers an entire side face and an entire upper face of the redistribution layer and a region of the redistribution layer where the spheroidal outer connection electrode is to be connected is exposed.

18. The method of claim 11 , further comprising individuating the semiconductor device after forming the spheroidal outer connection electrode.

19. The method of claim 11 , wherein to form the spheroidal outer connection electrode the method comprises forming the spheroidal outer connection electrode radially outside of the bump electrode as measured form a center of the semiconductor chip.

20. The method of claim 11 , wherein to fix the semiconductor chip to an upper face of the substrate the method comprises forming a fixing portion from epoxy resin that is coextensive with and fixed to a lower face of the semiconductor chip, wherein the fixing portion is encapsulated by the molding portion at both sides and the substrate at a bottom of the fixing portion.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2015
From: SPANSION LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 035891/0086 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2008
From: ONODERA, MASANORI; KASAI, JUNICHI
To: SPANSION LLC
Reel/Frame 020968/0538 →
Priority Claims (1)
JP 2007-048693 · Feb 28, 2007 · national
Continuity (1)
Related Publication 20090072394A1 · Mar 19, 2009