IP Library Granted Patent US 7,875,805
Granted Patent B2
US 7,875,805 · App. 12/039,997 · Granted Jan 25, 2011

Warpage-proof circuit board structure

Assignee: Unimicron Technology Corp.
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Quick Facts
Patent No.
US 7,875,805
App. No.
12/039,997
Granted
Jan 25, 2011
Kind
B2
Abstract

The invention provides a warpage-proof circuit board structure, including: an inner layer circuit board; at least one dielectric layer formed on at least one surface of the inner layer circuit board; at least one first groove formed in the at least one dielectric layer corresponding in position thereto; a solder mask formed on the surface of the dielectric layer, a second groove formed in the solder mask and corresponding in position to the first groove formed in the dielectric layer; and a metal frame formed in the first and second grooves and protruding from the surface of the solder mask, thereby strengthening the circuit board to prevent it from warping in thermal processing and further using the metal frame as a heat-dissipating means for the package structure.

Claims (17)

1. A warpage-proof circuit board structure, comprising:

an inner layer circuit board;

at least one dielectric layer formed on at least one surface of the inner layer circuit board and at least one first groove formed in the at least one dielectric layer corresponding in position thereto;

solder mask formed on the surface of the dielectric layer, a second groove formed in the solder mask and corresponding in position to the first groove in the dielectric layer;

a metal frame formed in the first and second grooves and protruding out of the surface of the solder mask, wherein the metal frame includes a first metal frame formed in the dielectric layer and a second metal frame formed in the solder mask;

a first electrical conductive layer formed between the dielectric layer and the first metal frame; and

a second electrical conductive layer formed between the solder mask and the second metal frame.

2. The warpage-proof circuit board structure of claim 1 , wherein the inner layer circuit board is one of two-layer and multi-layer circuit board with patterned circuit completed.

3. The warpage-proof circuit board structure of claim 1 , further including a build-up circuit layer formed on the dielectric layer, the build-up circuit layer electrically connecting the inner layer circuit board through electrical conductive vias formed in the dielectric layer.

4. The warpage-proof circuit board structure of claim 1 , further including a metal protecting layer formed on the surface of the metal frame.

5. The warpage-proof circuit board structure of claim 1 , wherein the first metal frame is one selected from the group consisting of tin, silver, copper, gold, bismuth, antimony, zinc, nickel, chromium, magnesium, indium, tellurium, and gallium.

6. The warpage-proof circuit board structure of claim 1 , wherein the second metal frame is one selected from the group consisting of tin, silver, copper, gold, bismuth, antimony, zinc, nickel, chromium, magnesium, indium, tellurium, and gallium.

7. The warpage-proof circuit board structure of claim 1 , wherein the first and second grooves are rectangular in shape.

8. The warpage-proof circuit board structure of claim 3 , wherein a portion of the build-up circuit layer in the dielectric layer is in the region surrounded by the first metal frame.

9. The warpage-proof circuit board structure of claim 3 , wherein openings are formed in the solder mask in the region surrounded by the second metal frame for exposing a portion of the build-up circuit layer so as to be electrically connecting pads.

10. The warpage-proof circuit board structure of claim 9 , further including metal posts disposed on the electrically connecting pads.

11. The warpage-proof circuit board structure of claim 1 , further including an independent washer formed at a position close to the periphery of the at least one surface of the inner layer circuit board and corresponding in position to the metal frame.

Assignments (3)
MERGER Recorded Dec 8, 2010
From: PHOENIX PRECISION TECHNOLOGY CORPORATION
To: UNIMICRON TECHNOLOGY CORP.
Reel/Frame 025478/0840 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 020581 FRAME 0128. ASSIGNOR(S) HEREBY CONFIRMS THE WEI-HUNG LIN, ASSIGNOR ASSIGNS US PATENT APPLICATION 12/039,997 TO PHOENIX PRECISION TECHNOLOGY CORPORATION, ASSIGNOR. Recorded Mar 3, 2008
From: LIN, WEI-HUNG
To: PHOENIX PRECISION TECHNOLOGY CORPORATION
Reel/Frame 020592/0013 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 29, 2008
From: LIN, WE-HUNG
To: PHOENIX PRECISION TECHNOLOGY CORPORATION
Reel/Frame 020581/0128 →
Priority Claims (1)
TW 96107115 A · Mar 2, 2007 · national
Continuity (1)
Related Publication 20080210459A1 · Sep 4, 2008