Process for making contact with and housing integrated circuits
View Patent ↗A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages.
1. A process comprising:
processing a semiconductor wafer, the semiconductor wafer having a top side and a bottom side, to form on the top side at least one optical element and means for making electrical contact with the at least one optical element, the electrical contact means being on the top side and having a bottom surface facing the top side of the semiconductor wafer;
before dicing, substantially thinning the semiconductor wafer;
forming a via in the semiconductor wafer after thinning the semiconductor wafer, the via extending from the bottom side of the semiconductor wafer to the bottom surface of the electrical contact means, the via having side walls;
forming an insulation layer on the side walls of the via; and
depositing metal in the via to produce an electrical contact between the bottom surface of electrical contact means and the bottom side of the semiconductor wafer.
2. The process according to claim 1 , further comprising fixing a transparent cover to the top side of the semiconductor wafer prior to conducting the thinning step.
3. The process according to claim 2 , wherein the fixing step comprises adhesively bonding the transparent cover to the semiconductor wafer.
4. The process according to claim 3 , wherein the adhesively bonding step comprises forming an epoxy resin layer between the semiconductor wafer and the transparent cover.
5. The process according to claim 1 , further comprising:
forming at least one bottom side electrical contact on the bottom side of the semiconductor wafer; and
electrically connecting the bottom side electrical contact to the metal in the via.
6. The process according to claim 1 , further comprising dicing the semiconductor wafer.
7. The process according to claim 1 , wherein said depositing step comprises depositing a layer of metal onto the insulation layer on the side walls of the via.
8. The process according to claim 1 , wherein the thinning step comprises thinning the semiconductor wafer to less than 200 microns.
9. The process according to claim 1 , wherein the step of forming the via comprises etching.