Busy detection logic for asynchronous communication port

1. An interface circuit comprising:

trigger logic for determining port busy information in response to a resource address and a read/write signal;

synchronization logic coupled to said trigger logic to receive said port busy information, said synchronization logic to synchronize said port busy information with a different time domain;

load logic clocked by a clock in said different time domain to communicate said port busy information from said synchronization logic to a resource access synchronizer to block receipt by said resource access synchronizer of subsequent port busy information; and

clear request logic to clear said port busy information from said trigger logic, said synchronization logic and said load logic.

2. The interface circuit of claim 1 , wherein said trigger logic is coupled to a processor to receive said resource address.

3. The interface circuit of claim 2 , wherein said clear request logic is operable under control of the processor.

4. The interface circuit of claim 1 , wherein said trigger logic generates port busy information on a rising edge of said read/write signal.

5. The interface circuit of claim 1 , wherein said port is a Universal Serial Bus (USB) end point.

6. The interface circuit of claim 1 , further comprising a core clock to clock said synchronization logic and said load logic.

7. The interface circuit of claim 1 , wherein said trigger logic comprises registers.

8. A method, comprising:

issuing an access request by a processor for access to an address of one of a plurality of resources in an independent time domain;

synchronizing resource information of said one resource to the independent time domain associated with said one resource;

transmitting said resource information to a resource synchronizing system to synchronize access to said address of said one resource, and preventing receipt by said resource synchronizing system of subsequent access request information; and

clearing resource information of said one resource after said one resource has been accessed by said processor.

9. The method of claim 8 , wherein said resource is a memory location.

10. The method of claim 8 , wherein said resource includes a pre-fetch buffer.

11. The method of claim 8 , wherein said resource to be accessed is determined based on address information.

12. The method of claim 8 , wherein said request to access a resource is a read request.

13. The method of claim 8 , wherein said request to access a resource is a write request.

14. The method of claim 8 , wherein said resource is a Universal Serial Bus (USB) end point.

15. A system comprising:

a processor configured to perform computing operations including memory access request addresses;

a memory device configured to store data;

memory interface logic coupled to the processor and configured to forward memory access requests information from the processor to a memory access synchronizer; and

busy detection logic coupling the memory interface logic and the memory access synchronizer to synchronize a current memory access request information from the processor with a time domain associated with the memory device, and to prevent information from another memory access request from being forwarded to the memory access synchronizer until said current memory access request information has been cleared from the busy detection logic.

16. The system of claim 15 , wherein said busy detection logic is also configured to clear resource information when access to said resource is completed.

17. The system of claim 15 , wherein the time domain associated with the memory device comprises a clock for the memory device.