Method of manufacturing a metal-oxide-semiconductor with reduced on-resistance
View Patent ↗The trench MOS transistor according to the present invention includes a drain region in a form of a trench filled with a semiconductor material. The trench has a bottom surface and side surfaces and extends vertically downward from the top surface of the covering layer into the buried layer, the bottom surface of the trench lies in the buried layer, an insulating layer lines the side surfaces of the trenches, and the semiconductor material within the trench overlies the insulating layer and contacts the buried layer at the bottom surface of the trench.
1. A method of manufacturing a metal-oxide-semiconductor (MOS) transistor, comprising:
providing a substrate;
forming a buried layer of a heavily doped first conductivity type on the substrate;
forming a covering layer of the first conductivity type on the buried layer;
forming a body region of a second conductivity type in the covering layer;
forming a trench having a bottom surface and side surfaces and extending vertically downward from the top surface of the covering layer into the buried layer, wherein the bottom surface of the trench lies in the buried layer;
performing an etching back process to remove the liner oxide on the bottom surface but not on the side surfaces of the trench;
forming a liner oxide on the side surfaces and the bottom surface of the trench;
filling a semiconductor material of the first conductivity type as a source/drain region within the trench to contact the buried layer at the bottom surface of the trench, leaving a space in the top portion of the trench;
forming a gate on the body region and the covering layer; and
forming a source/drain region within the body region.
2. The method of claim 1 , before filling the semiconductor material within the trench, further comprising:
performing a blanket heavily N type implantation on the surface of the buried layer in the trench.
3. The method of claim 1 , before forming the trench having a bottom surface and side surfaces, further comprising:
forming a cap layer on the covering layer to cover the body region.
4. The method of claim 3 , wherein the cap layer comprises an oxide layer and a nitride layer.
5. The method of claim 1 , wherein forming a gate on the body region and the covering layer comprises:
forming a gate dielectric layer on the body region and the covering layer; and
forming a gate electrode on the gate dielectric layer.
6. The method of claim 1 , further comprising forming a shallow trench insulation in the space in the top portion of the trench.