Clock generator, method for generating clock signal and fractional phase lock loop thereof

1. A clock generator, comprising:

a delta-sigma modulator configured to sequentially generate a plurality of variable parameters and a counting value according to a predetermined value and a first input clock signal;

a counter coupled to the delta-sigma modulator for generating an output clock signal according to the counting value and a second input clock signal, wherein the delta-sigma modulator does not reactivate output of the variable parameters until the output clock signal is fed back to the delta-sigma modulator; and

a phase lock loop coupled to the counter for generating an objective clock signal according to the output clock signal, comprising:

a charge pump configured to provide a first current with a current level; and

an additional current source coupled to the charge pump for providing a second current, wherein the current level is affected by the second current for generating a direct current offset such that the clock generator averts from a non-linear region, the objective clock signal is not fed back to the delta-sigma modulator and the counter.

2. The clock generator of claim 1 , wherein the delta-sigma modulator further receives the output clock signal, and generates the variable parameters in accordance with the output clock signal.

3. The clock generator of claim 1 , wherein the first phase lock loop is an integral phase lock loop having an integral frequency-dividing parameter, and the frequency of the objective clock signal is the product of an equivalent frequency of the output clock signal and the integral frequency-dividing parameter.

4. The clock generator of claim 1 , wherein the variable parameter is a digital signal for representing an integral value.

5. The clock generator of claim 1 , wherein the average value of the plurality of variable parameters is equal or close to the non-integral value represented by the pre-determined value.

6. The clock generator of claim 1 , wherein the first phase lock loop includes an integral frequency-dividing unit for generating a feedback signal required by the first phase lock loop by dividing the frequency of the objective clock signal by an integral value.

7. The clock generator of claim 1 , wherein the first input clock signal is different from the second input clock signal.

8. The clock generator of claim 1 , wherein the first phase lock loop is in an active manner without generating a feedback signal to the delta-sigma modulator or the counter.

9. The clock generator of claim 1 , further comprising a second phase lock loop for generating the first or second input clock signal in accordance with a reference clock signal, wherein the frequency of the reference clock signal is smaller than the frequency of the first or the second clock signal.