High surface area aluminum bond pad for through-wafer connections to an electronic package

1. An arrangement, comprising:

a bond pad effectuating a through-wafer connection to an integrated circuit chip or electronic package; and

said bond pad incorporating a high surface contact area forming a low-electrical resistance connection between said bond pad and electrical leads of said integrated circuit or electronic package;

wherein said high surface contact area comprises via bars formed at a bottom surface of said bond pad for increasing the contact area of said bond pad, and said bond pad includes a diagonal edge, said diagonal edge being formed using an isotropic etch so as to increase an electrical side contact surface of said bond pad;

wherein said via bars contact said bottom surface of said bond pad, and at least one of said via bars is connected to a vertically extending via which extends to a lower via bar in said arrangement.

2. An arrangement comprising a bond pad as claimed in claim 1 , wherein said bond pad is constituted of aluminum and said via bars are constituted of materials which are resistant to corrosion from applicable ambient conditions, and which are selected from the group of metals consisting of tungsten, a combination of tungsten and aluminum, Cr, Au, Ni, NiMoP, Co, CoWP or CoWB.

3. An arrangement comprising a bond pad as claimed in claim 1 , wherein a plurality of said bond pads are each connected to electrical leads, a plurality of slotted said vias being arranged below each of said bond pads, and via bars constituted of materials which are resistant to corrosion from applicable ambient conditions, and which are selected from the group of metals consisting of tungsten or a combination of tungsten and aluminum, Cr, Au, Ni, NiMoP, Co, CoWP or CoWB, being located in each of said vias for increasing the contact areas of said bond pads.

4. An arrangement comprising a bond pad as claimed in claim 1 , wherein a metal mask-forming layer is provided on the surface of said bond pad, and the surface area of said bond pad is increased.

5. An arrangement comprising a bond pad as claimed in claim 4 , wherein a shadow mask provides said metal mask-forming layer of evaporated metal to be deposited on the surface of said bond pad, or said metal is deposited by a selective plating process, such as electroplating or electroless plating.

6. An arrangement comprising a bond pad as claimed in claim 4 , wherein said mask-forming layer is consisting of a metal selected from the group of materials consisting of aluminum, gold, silver, silicon-based solder, lead-based solder, palladium, platinum, chromium, nickel, copper or alloys of said materials.

7. An arrangement of claim 1 , wherein said vertically extending via defines slots which include said via bars being arranged below another bond pad, and an electrical lead connects said another bond pad to said electronic package.

8. An integrated circuit chip, comprising:

a side chip surface, a bond pad having a first surface extending coplanarly with said side chip surface; and

an electrical lead extending adjacent to said bond pad, said electrical lead includes a surface extending coplanarly with said side chip surface so as to increase a contact surface area for electrical coupling to said bond pad forming a low-electrical resistance connection therebetween;

wherein said increased surface contact area comprises via bars formed at a bottom surface of said bond pad for increasing the contact area of said bond pad, and said bond pad includes a diagonal edge, said diagonal edge being formed using an isotropic etch so as to increase an electrical side contact surface of said bond pad;

wherein said via bars contact said bottom surface of said bond pad, and at least one of said via bars is connected to a vertically extending via which extends to a lower via bar in the arrangement.

9. An integrated circuit chip as claimed in claim 8 , wherein said bond pad is constituted of aluminum and said via bars are constituted of materials which are resistant to corrosion from applicable ambient conditions, and which are selected from the group of metals consisting of tungsten, a combination of tungsten and aluminum, Cr, Au, Ni, NiMoP, Co, CoWP or CoWB.

10. An integrated circuit chip as claimed in claim 8 , wherein a plurality of said bond pads are each connected to electrical leads, a plurality of slotted said vias being arranged below each of said bond pads, and via bars constituted of materials which are resistant to corrosion from applicable ambient conditions, and which are selected from the group of metals consisting of tungsten, a combination of tungsten and aluminum, Cr, Au, Ni, NiMoP, Co, CoWP or CoWB, being located in each of said vias for increasing the contact areas of said bond pads.

11. An integrated circuit chip as claimed in claim 8 , wherein a metal mask-forming layer is provided on the surface of said bond pad, and the surface area of said bond pad is increased by evaporation of metal through a shadow mask, or by selective plating processes, such as electroplating or electroless plating.