Method of manufacturing semiconductor device

1. A method of manufacturing a semiconductor device comprising a PMOS transistor and a NMOS transistor, comprising:

forming a silicon layer over a substrate through a gate insulating film;

forming a first gate electrode and second gate electrode by patterning said silicon layer, said first gate electrode being a gate electrode of said NMOS transistor, and said second gate electrode being a gate electrode of said PMOS transistor;

forming an interlayer film covering said first and said second gate electrodes;

planarizing said interlayer film;

removing an upper portion of said planarized interlayer film to expose said silicon layer of said first and said second gate electrodes;

simultaneously introducing impurity for controlling composition of a silicide phase, into said exposed upper portion of said silicon layer of said first and said second gate electrode respectively;

selectively removing said exposed upper portion of said second gate electrode having the introduced impurity, out of said first and said second gate electrodes;

forming a metallic layer formed of a metal capable of forming a silicide over said silicon layer of said selectively removed second gate electrode and said silicon layer of said first gate electrode;

performing a heat treatment such that a silicide layer of said metallic layer is formed; and

removing an unreacted portion of said metallic layer after said heat treatment process.

2. The method according to claim 1 , wherein said introducing impurity for controlling composition of a silicide phase into said silicon layer is executed between said removing an upper portion of said interlayer film and said selectively removing an upper portion of said second gate electrode.

3. The method according to claim 2 , wherein said introducing impurity for controlling composition of a silicide phase into said silicon layer excludes a heat treatment process that diffuses said impurity.

4. The method according to claim 1 , wherein said introducing impurity for controlling composition of a silicide phase includes introducing said impurity in high concentration into said silicon layer to a depth corresponding to equal to or more than 0 and equal to or less than 0.5 times of a thickness of said silicon layer from a surface thereof, and said selectively removing includes removing a portion of said silicon layer containing said impurity of said high concentration.

5. The method according to claim 1 , wherein said impurity for controlling composition of said silicide phase includes at least one selected from the group consisting of As, P, Sb, B, BF 2 , and F.

6. The method according to claim 5 , wherein said impurity for controlling composition of said silicide phase is B, and an implantation amount thereof is equal to or more than 8×10 15 cm −2 in surface density.

7. The method according to claim 1 , wherein said introducing impurity for controlling composition of a silicide phase into said silicon layer includes:

introducing a first impurity into said silicon layer between said forming a silicon layer and said forming an interlayer film, and diffusing said first impurity throughout an entirety of said silicon layer by a heat treatment process; and

introducing a second impurity into said silicon layer between said entirely removing and said selectively removing;

wherein said introducing a second impurity excludes diffusing said second impurity.

8. The method according to claim 7 , wherein said introducing a second impurity includes introducing said second impurity in high concentration into said silicon layer to a depth corresponding to equal to or more than 0 and equal to or less than 0.5 times of a thickness of said silicon layer from a surface thereof; and said selectively removing includes removing a portion of said silicon layer containing said impurity of said high concentration.

9. The method according to claim 7 , wherein said heat treatment process to diffuse said first impurity is an impurity activation process.

10. The method according to claim 7 , wherein said first and said second impurity for controlling composition of said silicide phase are different from each other, and respectively include at least one selected from the group consisting of As, P, Sb, B, BF 2 , and F.

11. The method according to claim 10 , wherein said first impurity for controlling composition of said silicide phase includes As, and an implantation amount of As is equal to or less than 5×10 15 cm −2 in surface density, and said second impurity includes B, and an implantation amount of B makes a total of equal to or more than 8×10 15 cm −2 in surface density, including said implantation amount of As.

12. The method according to claim 1 , wherein said gate insulating layer includes HfSiON x at least on an upper surface thereof.

13. The method according to claim 1 , wherein said heat treatment process turns a region of said silicon layer of said gate electrode for said PMOS transistor in contact with said gate insulating layer into one of Ni 3 Si and Ni 31 Si 12 , and turns a region of said silicon layer of said gate electrode for said NMOS transistor in contact with said gate insulating layer into one of NiSi 2 and NiSi.

14. The method according to claim 1 , comprising executing said heat treatment process at a temperature of 500° C. or lower.

15. The method according to claim 1 , wherein said impurity for controlling composition of said silicide phase includes As, and said heat treatment process includes:

a first heat treatment process that forms a first silicide phase;

a second heat treatment process that forms an oxide layer only on a surface of said first silicide phase containing As;

a third heat treatment process that forms a second silicide phase without removing an unreacted portion of said metallic layer; and

removing said unreacted portion of said metallic layer, and further removing said oxide layer, after said third heat treatment process.