IP Library Granted Patent US 7,999,246
Granted Patent B2
US 7,999,246 · App. 12/048,819 · Granted Aug 16, 2011

Semiconductor memory device and method of manufacturing the same

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Quick Facts
Patent No.
US 7,999,246
App. No.
12/048,819
Granted
Aug 16, 2011
Kind
B2
Abstract

A semiconductor memory device includes a first resistance change element having a first portion and a second portion, the first portion and the second portion having a first space in a first direction, and a second resistance change element formed to have a distance to the first resistance change element in the first direction, and having a third portion and a fourth portion, the third portion and the fourth portion having a second space in the first direction, and the first space and the second space being shorter than the distance.

Claims (29)

1. A semiconductor memory device comprising:

a first resistance change element having a first portion and a second portion, the first portion and the second portion having a first space in a first direction; and

a second resistance change element formed to have a distance to the first resistance change element in a second direction perpendicular to the first direction, and having a third portion and a fourth portion, the third portion and the fourth portion having a second space in the first direction, and the first space and the second space being shorter than the distance,

the first portion, the second portion, the third portion and the fourth portion being separated physically.

2. The device according to claim 1 , wherein each of the first resistance change element and the second resistance change element comprises one of:

a magnetoresistive effect element having a fixed layer in which a magnetization direction is fixed, a recording layer in which a magnetization direction reverses, and a nonmagnetic layer sandwiched between the fixed layer and the recording layer;

a resistance change element using a CER effect; and

a phase change element using a crystal phase change.

3. The device according to claim 1 , wherein

the first resistance change element further has a fifth portion and a sixth portion,

the second resistance change element further has a seventh portion and an eighth portion,

the first portion, the second portion, the fifth portion, and the sixth portion are separately arranged at apexes of a quadrangle, and

the third portion, the fourth portion, the seventh portion, and the eighth portion are separately arranged at apexes of a quadrangle.

4. The device according to claim 3 , wherein

the first portion and the fifth portion have a third space in the second direction,

the third portion and the seventh portion have a fourth space in the second direction, and

the third space and the fourth space are shorter than the distance.

5. The device according to claim 4 , wherein the first space, the second space, the third space, and the fourth space are equal.

6. The device according to claim 1 , wherein the first portion, the second portion, the third portion, and the fourth portion are linear shapes extending in the second direction.

7. The device according to claim 6 , wherein a length in the second direction of each of the first portion, the second portion, the third portion, and the fourth portion is equal to the distance.

8. A semiconductor memory device comprising:

a plurality of resistance change elements including a first resistance change element and a second resistance change element formed apart from the first resistance change element in a first direction, the plurality of resistance change elements being included in respective cells and being separated physically;

a first contact connected to the first resistance change element and having a first portion and a second portion, the first portion and the second portion having a first space in the first direction; and

a second contact connected to the second resistance change element, formed to have a distance to the first contact in the first direction, and having a third portion and a fourth portion, the third portion and the fourth portion having a second space in the first direction, and the first space and the second space being shorter than the distance.

9. The device according to claim 8 , wherein

the first contact further has a fifth portion and a sixth portion,

the second contact further has a seventh portion and an eighth portion,

the first portion, the second portion, the fifth portion, and the sixth portion are separately arranged at apexes of a quadrangle, and

the third portion, the fourth portion, the seventh portion, and the eighth portion are separately arranged at apexes of a quadrangle.

Assignments (4)
DE-MERGER Recorded Dec 12, 2019
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051260/0291 →
MERGER Recorded Dec 12, 2019
From: TOSHIBA MEMORY CORPORATION; K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 051262/0776 →
CHANGE OF NAME AND ADDRESS Recorded Dec 12, 2019
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 051262/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2008
From: IWAYAMA, MASAYOSHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 020958/0532 →