Semiconductor device and method for manufacturing the same
View Patent ↗It is disclosed a semiconductor device including a silicon substrate, provided with a plurality of cell active regions in a call region, an element isolation groove, formed in a portion, between any two of the plurality of cell active region, of the silicon substrate, a capacitor dielectric film, formed in the element isolation groove, a capacitor upper electrode, formed on the capacitor dielectric film, and configuring a capacitor together with the silicon substrate and the capacitor dielectric film. The semiconductor device is characterized in that a dummy active region is provided next to the cell region in the silicon substrate.
1. A semiconductor device, comprising:
a semiconductor substrate provided with a plurality of cell active regions in a cell region, the semiconductor substrate being provided with a peripheral circuit region;
an element isolation groove formed in the semiconductor substrate between the cell active regions, the element isolation groove also being formed in the semiconductor substrate in the peripheral circuit region;
an element isolation insulating film formed in the element isolation groove in the peripheral circuit region, the element isolation insulating film having a thickness to substantially fill the element isolation groove in the peripheral circuit region;
a capacitor dielectric film formed in the element isolation groove; and
a capacitor upper electrode, formed over the capacitor dielectric film, and constituting a capacitor together with the semiconductor substrate and the capacitor dielectric film,
wherein a dummy active region is provided in the semiconductor substrate beside the cell region.
2. The semiconductor device according to claim 1 , further comprising a gate electrode of a MOS transistor, the gate electrode being formed over the cell active regions with a gate insulating film interposed therebetween, wherein
a one transistor-one capacitor memory cell is constructed from the capacitor and the MOS transistor.
3. The semiconductor device according to claim 2 , wherein an interval between the dummy active region and the cell active region at an end portion of the cell region is narrower than a width of the memory cell.
4. The semiconductor device according to claim 2 , wherein the dummy active region is in a stripe shape extending in a repeating direction of the memory cell.
5. The semiconductor device according to claim 1 , wherein the dummy active region is formed independently from the cell active regions.
6. A semiconductor device, comprising:
a semiconductor substrate provided with a plurality of active regions in a cell region;
a well formed in the semiconductor substrate in the cell region;
an element isolation groove formed in the semiconductor substrate between the active regions;
an impurity diffusion region formed in the semiconductor substrate under the element isolation groove, the impurity diffusion region being the same conductivity type as that of the well;
a capacitor dielectric film formed in the element isolation groove; and
a capacitor upper electrode, formed over the capacitor dielectric film, and constituting a capacitor together with the semiconductor substrate and the capacitor dielectric film,
wherein the film thickness of the capacitor dielectric film on a bottom surface of the element isolation groove is larger in an end portion of the cell region as compared with in other portions than the end portion of the cell region.
7. The semiconductor device according to claim 6 , wherein
a recessed portion is formed in an upper surface of the capacitor dielectric film in the element isolation groove, and,
in the end portion of the cell region, a peak of an impurity concentration of the impurity diffusion region is positioned in the bottom surface of the element isolation groove, the bottom surface being under the recessed portion.
8. The semiconductor device according to claim 6 , wherein
a peripheral MOS transistor is formed in a peripheral circuit region of the semiconductor substrate, and
the impurity diffusion region is formed as an impurity diffusion region for adjusting a threshold voltage in the peripheral circuit region of the semiconductor substrate.
9. A semiconductor device, comprising:
a semiconductor substrate provided with a plurality of active regions in a cell region;
a well formed in the semiconductor substrate in the cell region;
an element isolation groove formed in the semiconductor substrate between the active regions;
a channel stop region formed in the semiconductor substrate under the element isolation groove, a conductivity type of the channel stop region being the same as that of the well;
a capacitor dielectric film formed in the element isolation groove; and
a capacitor upper electrode, formed over the capacitor dielectric film, and constituting a capacitor together with the semiconductor substrate and the capacitor dielectric film, wherein
an impurity concentration of the channel stop region is higher in an end portion of the cell region as compared with in a portion of the channel stop region other than the end portion of the cell region.
10. The semiconductor device according to claim 9 , wherein a recessed portion is formed in an upper surface of the capacitor dielectric film in the element isolation groove, and,
in the end portion of the cell region, a peak of an impurity concentration of the channel stop region is positioned in a bottom surface of the element isolation groove, the bottom surface being under the recessed portion.