IP Library Granted Patent US 8,105,935
Granted Patent B2
US 8,105,935 · App. 12/051,193 · Granted Jan 31, 2012

Method of manufacturing a semiconductor device

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Quick Facts
Patent No.
US 8,105,935
App. No.
12/051,193
Granted
Jan 31, 2012
Kind
B2
Abstract

A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a silicon-containing gas, performing a plasma treatment of the surface of the metal interconnect after exposing to the silicon-containing gas, and forming a second insulating film over the metal interconnect.

Claims (33)

1. A method of manufacturing a semiconductor device comprising:

forming a first insulating film over a semiconductor substrate;

forming a trench in the first insulating film;

forming a first metal interconnect including copper in the trench;

exposing the upper surface of the metal interconnect to an organic type silane gas and siliconizing the upper surface of the metal interconnect;

after exposing of the upper surface of the first metal interconnect to the organic type silane gas, performing a plasma treatment to the siliconized surface of the first metal interconnect to form a silicon-containing layer including silicon and copper in the upper surface of the first metal interconnect;

after performing of the plasma treatment, forming a second insulating film on and in contact with the silicon-containing layer; and

forming a second metal interconnect in the second insulating film and in contact with the upper surface of the first metal interconnect,

wherein the plasma treatment is performed using at least one selected from a group consisting of nitrogen, hydrogen, dinitrogen monoxide, carbon dioxide, oxygen, and hydrocarbons.

2. The method according to claim 1 , further comprising:

performing a reducing plasma treatment of the first metal interconnect after forming the metal interconnect and prior to exposing to the silicon-containing gas.

3. The method according to claim 2 , wherein the reducing plasma treatment is performed at 300° C. to 450° C.

4. The method according to claim 1 , wherein the organic type silane gas includes at least one selected from a group consisting of tetramethylsilane, trimethylsilylacetylene, trimethylsilane, dimethylsilane, tetramethoxysilane, dimethyldimethoxysilane, tetramethylcyclotetrasiloxane, octamethylcyclotetrasiloxane, dimethyldiethoxysilane, dimethylphenylsilane, diphenyldimethoxysilane, diphenyldiethoxysilane, phenyldiethoxysilane, and diethoxymethylsilane.

5. The method according to claim 1 , wherein the surface of the metal interconnect is exposed to the silicon-containing gas after dilution of the silicon-containing gas with at least one selected from a group consisting of nitrogen, ammonia, hydrogen, noble gases, and hydrocarbons.

6. The method according to claim 1 , wherein a time interval of exposing of the upper surface of the first metal interconnect to the silicon-containing gas is 1 sec. to 60 sec.

7. The method according to claim 1 , wherein a time interval of the plasma treatment is 3 sec. to 60 sec.

8. The method according to claim 1 , wherein

the first metal interconnect includes copper, and

a silicon-containing layer containing copper, silicon, oxygen, nitrogen, and carbon is formed over the first metal interconnect by the plasma treatment.

9. The method according to claim 8 , wherein a layer thickness of the silicon-containing layer is 0.1 nm to 10 nm.

10. The method according to claim 1 , wherein

the first metal interconnect includes copper, and

a silicon-containing layer containing copper, silicon, oxygen, and carbon is formed over the first metal interconnect by the plasma treatment.

11. The method according to claim 10 , wherein a layer thickness of the silicon-containing layer is 0.1 nm to 10 nm.

12. The method according to claim 1 , wherein the second insulating film includes at least one selected from a group consisting of silicon nitride, oxygen-containing silicon carbide, nitrogen-containing silicon carbide, silicon carbide, carbon-containing silicon oxide, and boron nitride.

13. The method according to claim 1 ,

a first AC voltage is applied to a top electrode, and a second AC voltage is applied to a bottom electrode in a plasma generation apparatus;

the semiconductor substrate is disposed on the bottom electrode; and

the plasma treatment is performed.

14. The method according to claim 13 , wherein a first frequency of the first AC voltage is 10 MHz to 300 MHz.

15. The method according to claim 13 , wherein a first power of the first AC voltage is 0.02 W·cm −2 to 0.8 W·cm −2 .

16. The method according to claim 13 , wherein the second AC voltage has a second power less than or equal to 1.6 W·cm −2 and a second frequency lower than the first frequency.

17. The method according to claim 16 , wherein the second frequency is 100 KHz to 500 KHz.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2008
From: OHARA, NAOKI; WATATANI, HIROFUMI; OWADA, TAMOTSU; YANAI, KENICHI
To: FUJITSU LIMITED
Reel/Frame 020702/0439 →