Waveform generator and test apparatus
View Patent ↗The purpose is to provide a waveform generator that generates signals with a frequency lower than the minimum sampling frequency of the DAC. In the waveform generator 10 , the clock generator 106 generates a clock signal 140 . The frequency divider 112 divides the frequency of the clock signal 140 and generates the frequency-divided clock signal 144 . The reader 118 provides an address signal at the period of frequency-divided clock signal 144 for the waveform memory 120 and reads the pattern data from the waveform memory 120 into the DAC 130 . The DAC 130 converts the data provided from the waveform generator 120 at the period of clock signal 140 into an analog value and outputs a waveform of arbitrary shape.
1. A waveform generator for generating a waveform, comprising:
a memory operative to retain pattern data indicating a pattern of a waveform;
a clock signal generator operative to generate a clock signal;
a reader operative to read the pattern data from the memory at a frequency obtained by dividing the frequency of the clock signal; and
a digital-to-analog converter operative to receive the pattern data read at a divided frequency and subject the pattern data to digital-to-analog conversion at the frequency of the clock signal so as to output a waveform having same value over a period defined by the divided frequency and varying in level at the divided frequency.
2. The waveform generator according to claim 1 further comprising a frequency divider operative to divide the frequency of the clock signal.
3. The waveform generator according to claim 2 , wherein
the frequency divider divides the frequency of the clock signal by thinning out the pulses of the clock signals.
4. A test apparatus including a waveform generator for providing a test waveform to a device to be tested, wherein the waveform generator comprises:
a memory operative to retain pattern data indicating a pattern of a waveform;
a clock signal generator operative to generate a clock signal;
a reader operative to read the pattern data from the memory at a frequency obtained by dividing the frequency of the clock signal; and
a digital-to-analog converter operative to receive the pattern data read at a divided frequency and subject the pattern data to digital-to-analog conversion at the frequency of the clock signal so as to output a waveform having same value over a period defined by the divided frequency and varying in level at the divided frequency.
5. The test apparatus according to claim 4 , wherein the waveform generator further comprises a frequency divider operative to divide the frequency of the clock signal.
6. The test apparatus according to claim 5 , wherein the frequency divider divides the frequency of the clock signal by thinning out the pulses of the clock signals.