Image capturing apparatus
An apparatus including: a photodiode including: a first conductivity substrate; a second conductivity PD-well on the substrate's first surface side; and a first conductivity collection well inside the PD-well; a modulation transistor including: a second conductivity TR-well connected with the PD-well, and a junction depth shallower than that of the PD-well; a first conductivity modulation well inside the TR-well, and connected with the collection well; a second conductivity source inside the modulation well, and including a region contacting the first surface; a gate electrode in a region partially covering the modulation well and enclosing the source; a gate insulation layer between the gate and the first surface; and a second conductivity drain partially sandwiching the gate and opposing the source, and including a region contacting the first surface; and a transfer transistor connected to modulation transistors in pixels between the source and a connected source line.
1. An Image capturing apparatus, comprising:
a first gate line formed in a first direction;
a first source line intersecting with the first gate line, the first gate line and the first source line defining a first pixel;
a common drain line;
a first photodiode formed in the first pixel, the first photodiode being connected to the common drain line;
a first modulation transistor formed in the first pixel, a first drain of the first modulation transistor being connected to the common drain line;
a second gate line formed in the first direction, the second gate line intersecting with the first source line, the second gate line and the first source line defining a second pixel;
a second photodiode formed in the second pixel, the second photodiode being connected to the common drain line;
a second modulation transistor formed in the second pixel, a second drain of the second modulation transistor being connected to the common drain line;
a first line formed in the first pixel and the second pixel, the first line connecting a first source of the first modulation transistor and a second source of the second modulation transistor; and
a transfer transistor formed between the first source line and the first line, the transfer transistor being connected to the first source line, to the first line, and to a third gate line, the third gate line being formed in the first direction and intersecting with the first source line.
2. The image capturing apparatus according to claim 1 , the transfer transistor being positioned between the first photodiode and the second photodiode.
3. The image capturing apparatus according to claim 1 , the first photodiode having a first aperture section, the first line being formed away from the first aperture section.
4. The image capturing apparatus according to claim 1 , a potential of the first source and the second source being configured to be transmitted to the first source line only when selected by the transfer transistor.
5. An Image capturing apparatus, comprising:
a first gate line formed in a first direction;
a first source line intersecting with the first gate line, the first gate line and the first source line defining a first pixel;
a common drain line;
a first photodiode formed in the first pixel, the first photodiode being connected to the common drain line;
a first modulation transistor formed in the first pixel, a first drain of the first modulation transistor being connected to the common drain line;
a second gate line formed in the first direction, the second gate line intersecting with the first source line, the second gate line and the first source line defining a second pixel;
a second photodiode formed in the second pixel, the second photodiode being connected to the common drain line;
a second modulation transistor formed in the second pixel, a second drain of the second modulation transistor being connected to the common drain line;
a first transfer transistor formed in the first pixel, the first transfer transistor being connected to a first source of the first modulation transistor, to a third gate line, and to the first source line; and
a second transfer transistor formed in the second pixel, the second transfer transistor being connected to a second source of the second modulation transistor, to a fourth gate line, and to the first source line.