Signal transmission circuit for increasing soft error tolerance
View Patent ↗A CAD device according to the embodiments includes means that determines signal transmission time of each signal transmission circuit in an LSI circuit, means that determines an output inversion rate of a flip-flop circuit included in each signal transmission circuit when the flip-flop circuit is exposed to radiation, means that determines a signal transmission circuit that is a critical path, means that calculates a total soft error rate of the LSI circuit on the basis of the signal transmission time, the output inversion rate, and a clock period, and means that, when a predetermined soft error rate is less than the total soft error rate of the LSI circuit as a result of comparison, reducing the total soft error rate of the LSI circuit to the extent possible without changing signal transmission time of the signal transmission circuit, which is a critical path.
1. A CAD device that implements a method for designing a semiconductor circuit device, the CAD device comprising:
a first determining unit determining signal transmission time necessary for each signal transmission circuit in an LSI circuit to transmit a signal;
a second determining unit determining a frequency distribution of the signal transmission time;
a detecting unit detecting the longest signal transmission time on the basis of the signal transmission time;
a third determining unit determining an output inversion rate at which the logic of an output signal from each flip-flop circuit is inverted on the basis of the amount of charge held in a critical node in each flip-flop circuit and a logic of input signal in each flip-flop;
a calculating unit calculating a soft error rate of the LSI circuit on the basis of the frequency distribution of the signal transmission time, an operating clock period, and the output inversion rate of each flip-flop circuit; and
a modifying unit, when a predetermined soft error rate is less than the soft error rate of the LSI circuit as a result of comparison, modifying the LSI circuit to the extent possible without changing the longest signal transmission time by changing the frequency distribution of the signal transmission time.
2. The CAD device according to claim 1 , wherein the CAD device that modifies the LSI circuit reduces the soft error rate of the LSI circuit by modifying a delay element that constitutes each signal transmission circuit.
3. The CAD device according to claim 2 , wherein each signal transmission circuit comprises:
a first flip-flop circuit;
a second flip-flop circuit; and
the delay element, which is disposed between an output terminal of the first flip-flop circuit and an input terminal of the second flip-flop circuit, transmits a signal from the output terminal to the input terminal after delaying the signal, and includes a dummy circuit, and
modifying the delay element, which constitutes each signal transmission circuit, means changing the dummy circuit to an inverter circuit.
4. The CAD device according to claim 2 , wherein each signal transmission circuit comprises:
a first flip-flop circuit;
a second flip-flop circuit; and
the delay element, which is disposed between an output terminal of the first flip-flop circuit and an input terminal of the second flip-flop circuit, transmits a signal from the output terminal to the input terminal after delaying the signal, and includes a capacitance, and
modifying the delay element, which constitutes each signal transmission circuit, is performed by increasing or decreasing the capacitance.
5. The CAD device according to claim 2 , wherein each signal transmission circuit comprises:
a first flip-flop circuit;
a second flip-flop circuit; and
the delay element, which is disposed between an output terminal of the first flip-flop circuit and an input terminal of the second flip-flop circuit, transmits a signal from the output terminal to the input terminal after delaying the signal, and includes a resistance, and
modifying the delay element, which constitutes each signal transmission circuit, is performed by increasing or decreasing the resistance.
6. The CAD device according to claim 1 , wherein the CAD device that modifies the LSI circuit modifies each flip-flop circuit so as to reduce the output inversion rate of each flip-flop circuit.
7. The CAD device according to claim 6 , wherein each signal transmission circuit comprises:
a first flip-flop circuit that includes a master flip-flop and a slave flip-flop;
a second flip-flop circuit; and
a delay element that is disposed between an output terminal of the first flip-flop circuit and an input terminal of the second flip-flop circuit, and transmits a signal from the output terminal to the input terminal after delaying the signal, and
modifying each flip-flop circuit means adding a capacitance to a critical node in the master flip-flop.
8. A method executed by a computer for designing a semiconductor circuit device aided by a CAD device, comprising:
determining, using said computer, signal transmission time necessary for each signal transmission circuit in an LSI circuit to transmit a signal;
determining a frequency distribution of the signal transmission time;
detecting the longest signal transmission time on the basis of the signal transmission time;
determining an output inversion rate at which the logic of an output signal from each flip-flop circuit is inverted on the basis of the amount of charge held in a critical node in each flip-flop circuit and a logic of input signal in each flip-flop;
calculating a soft error rate of the LSI circuit on the basis of the frequency distribution of the signal transmission time, an operating clock period, and the output inversion rate of each flip-flop circuit; and
modifying the LSI circuit to the extent possible without changing the longest signal transmission time when a predetermined soft error rate is less than the soft error rate of the LSI circuit as a result of comparison by changing the frequency distribution of the signal transmission time.