Interconnect structure encased with high and low k interlevel dielectrics
View Patent ↗A structure for improving the electrostatic discharge robustness of an integrated circuit having an electrostatic discharge (ESD) device and a receiver network connected to a pad by interconnects. The interconnect between the pad and the ESD device has a high-k material placed adjacent to at least one surface of the interconnect and extending over the thermal diffusion distance of the interconnect. The high-k material improves the critical current density of the interconnect by increasing the heat capacity and thermal conductivity of the interconnect. The high-k material can be placed on the sides, top and/or bottom of the interconnect. In multiple wire interconnects, the high-k material is placed between the wires of the interconnect. A low-k material is placed beyond the high-k material to reduce the capacitance of the interconnect. The combination of low-k and high-k materials provides an interconnect structure with improved ESD robustness and low capacitance that is well suited for an ESD device. The interconnect to the receiver, which does not carry a high current, is surrounded by a low-k material for reduced capacitance and performance advantages.
1. An integrated circuit apparatus, comprising:
an electrostatic discharge (ESD) device;
a pad; and
a wiring level on a substrate comprising:
an interconnect comprising a plurality of interconnect wires having a common electrical node electrically connecting said pad and said ESD device;
a high-k material substantially filling at least a region in between said interconnect wires, said region extending from a sidewall of one of said interconnect wires to a sidewall of an adjacent one of said interconnect wires, said high-k material for increasing an electrostatic discharge robustness of the interconnect; and
a low-k material adjacent to said interconnect and located outside of said region that is substantially filled by said high-k material for reducing a capacitance of the interconnect.
2. The integrated circuit apparatus according to claim 1 , wherein said high-k material is also disposed above or below said interconnect wires.
3. The integrated circuit apparatus according to claim 1 , wherein said high-k material surrounds said interconnect.
4. The integrated circuit apparatus according to claim 1 , wherein said high-k material is disposed between said low-k material and said interconnect.
5. The integrated circuit apparatus according to claim 1 , wherein said high-k material is SiO 2 .
6. The integrated circuit apparatus according to claim 1 , wherein said high-k material has a thickness equal to or greater than a thermal diffusion distance of said interconnect.
7. The integrated circuit apparatus according to claim 1 , wherein said high-k material has a dielectric constant, k, of higher than about 3.5.
8. The integrated circuit apparatus according to claim 1 , wherein said high-k material has a dielectric constant, k, of about 4.0.
9. The integrated circuit apparatus according to claim 1 , wherein said low-k material has a dielectric constant, k, of lower than about 3.5.
10. An interconnect structure, comprising:
a metal conductor comprising a plurality of interconnect wires having a common electrical node in a wiring level on a substrate;
a high-k material substantially filling at least a region in between said interconnect wires, said region extending from a sidewall of one of said interconnect wires to a sidewall of an adjacent one of said interconnect wires, said high-k material for increasing an electrostatic discharge robustness of the interconnect structure; and
a low-k material adjacent to said metal conductor and located outside of said region that is substantially filled by said high-k material for reducing a capacitance of the interconnect structure.
11. The interconnect structure according to claim 10 , wherein said metal conductor comprises a damascene copper interconnect wire or a dual damascene copper interconnect wire and via structure.
12. The interconnect structure according to claim 10 , wherein said high-k material is disposed between said low-k material and said metal conductor.