Method and apparatus for synchronous boost voltage regulators with active negative current modulation
A switch-mode synchronous boost voltage regulator is disclosed that includes a boost voltage regulator and an active current modulator. The active current modulator detects a negative current flowing through the high-side switch during a light load condition. When the negative current is detected, the active current modulator is operable to maintain the high-side switch “on” in a linear mode and to limit the negative current to a predetermined current level.
1. A circuit comprising:
a boost voltage regulator including a low-side switch and a high-side switch, the boost voltage regulator operable to generate a stabilized output voltage that is greater than an input voltage; and
an active current modulator electrically coupled to detect a negative current flowing through said high-side switch during a light load condition, wherein when said negative current flow is detected, said active current modulator is activated to maintain said high-side switch in an on state in a linear mode and to limit said negative current flow to a predetermined current level,
wherein said active current modulator further comprises;
a comparator circuit electrically coupled to said high-side switch, operable to detect said negative current; and
a current mirror circuit, electrically coupled to said comparator circuit and to said boost voltage regulator circuit, operable to force said negative current to be in a predetermined relation to said predetermined current level.
2. The circuit of claim 1 wherein said current mirror circuit further comprises a p-type Metal Oxide Semiconductor (pMOS) transistor electrically coupled to said high-side pMOS transistor switch.
3. The circuit of claim 2 wherein said comparator circuit further comprises a non-inverting input terminal, an inverting input terminal, and an output terminal, the inverting input terminal electrically coupled to the source of said pMOS transistor switch, the non-inverting input terminal electrically coupled to the drain of said pMOS transistor switch and to said inductor.
4. The circuit of claim 3 wherein said pMOS transistor is configured to be substantially smaller in size than said pMOS transistor switch.
5. The circuit of claim 4 wherein said current mirror circuit further comprises:
a second error amplifier circuit electrically coupled to said pMOS transistor switch;
a third error amplifier circuit electrically coupled to a second reference voltage and to said pMOS transistor switch; and
an SR flip flop circuit electrically coupled to said first gate driver circuit, said comparator circuit, and said third error amplifier circuit.
6. The circuit of claim 1 wherein said current mirror circuit further comprises:
a pnp bipolar junction transistor electrically coupled to said second error amplifier circuit and to said pMOS transistor switch; and
an output resistor electrically coupled to said pnp bipolar junction transistor and to an electrical ground.