Method for fabricating semiconductor structure and structure of static random access memory
View Patent ↗A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening.
1. A static random access memory comprising:
a substrate, wherein a first type doped region, a second type doped region, and an isolation structure separating the first type doped region and the second type doped region apart are formed therein;
an interlayer dielectric layer disposed on the substrate, the interlayer dielectric layer having an opening extending across the first type doped region, the isolation structure and the second doped region such that the substrate is exposed;
a high-k dielectric layer disposed in the opening along inner sidewalls and a bottom of the opening;
a first low resistance conductive layer disposed on the second type doped region and a portion of the isolation structure and filling in the opening;
a second type conductive layer disposed between the first low resistance conductive layer and the high-k dielectric layer;
a first type conductive layer disposed on the high-k dielectric layer along an exposed sidewall of the first low resistance conductive layer and an exposed upper surface of the high-K dielectric layer in the opening; and
a second low resistance conductive layer disposed on the first type conductive layer and filling in the opening.
2. The static random access memory in accordance with claim 1 , further comprising a dielectric layer disposed between the high-k dielectric layer and the substrate and between the high-k dielectric layer and the interlayer dielectric layer.
3. The static random access memory in accordance with claim 1 , wherein the first type doped region is a P-type doped region, and the second type doped region is an N-type doped region.
4. The static random access memory in accordance with claim 3 , wherein the first type conductive layer is a P-type conductive layer, and the second type conductive layer is an N-type metal layer.
5. The static random access memory in accordance with claim 4 , wherein material of the P-type metal layer comprises tungsten, tungsten nitride, platinum, titanium nitride or ruthenium.
6. The static random access memory in accordance with claim 4 , wherein material of the N-type metal layer comprises tantalum nitride, tantalum silicon nitride, tantalum carbide, titanium aluminum nitride, aluminum-titanium alloy, titanium aluminum compound or aluminum.
7. The static random access memory in accordance with claim 1 , wherein material of the high-k dielectric layer comprises tantalum oxide, Ba 1-x Sr x TiO 3 , silicon nitride, silicon oxynitride, silicon carbide, silicon carbon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium oxide, zirconium silicon oxide, zirconium hafnium oxide, titanium oxide, cerium oxide, lanthanum oxide, lanthanum aluminum oxide or aluminum oxide.