Semiconductor device
View Patent ↗A semiconductor device includes a substrate common to a first field effect transistor and a second field effect transistor, a channel layer of a first conductivity type formed on the substrate and common to the first and second field effect transistors, a an upper compound semiconductor layer formed on the channel layer and common to the first and second field effect transistors, a compound semiconductor region of a second conductivity type formed in the same layer as the upper compound semiconductor layer, a gate electrode of the first field effect transistor in ohmic contact with the compound semiconductor region, and a gate electrode of the second field effect transistor in Schottky contact with the upper compound semiconductor layer.
1. A semiconductor device, comprising:
a substrate common to a first field effect transistor and a second field effect transistor;
a channel layer of a first conductivity type formed on the substrate and common to the first and second field effect transistors;
an upper compound semiconductor layer formed on the channel layer and common to the first and second field effect transistors;
a compound semiconductor region of a second conductivity type formed in the same layer as the upper compound semiconductor layer;
a gate electrode of the first field effect transistor in ohmic contact with the compound semiconductor region at a position spaced apart from said upper compound semiconductor layer; and
a gate electrode of the second field effect transistor in Schottky contact with the upper compound semiconductor layer.
2. The semiconductor device according to claim 1 , further comprising:
an isolation layer for electrically isolating the first field effect transistor and the second field effect transistor.
3. The semiconductor device according to claim 1 , further comprising:
an electron supply layer common to the first and second field effect transistor; and
a spacer layer formed between the channel layer and the electron supply layer and common to the first and second field effect transistors.
4. The semiconductor device according to claim 1 , wherein the compound semiconductor region of second conductivity type is a regrown compound semiconductor layer that is deposited in a recess provided in the upper compound semiconductor layer.
5. The semiconductor device according to claim 1 , wherein the gate electrode of the second field effect transistor has a portion embedded in a recess provided in the upper compound semiconductor layer.
6. The semiconductor device according to claim 5 , wherein the gate electrode of the second field effect transistor does not abut the inner wall of the recess provided in the upper compound semiconductor layer.
7. The semiconductor device according to claim 1 , wherein the first field effect transistor is an enhancement-mode field effect transistor, and the second field effect transistor is a depletion-mode field effect transistor.
8. The semiconductor device according to claim 1 , wherein the first field effect transistor is a field effect transistor for a power amplifier circuit, and the second field effect transistor is a field effect transistor for a switching circuit.
9. The semiconductor device according to claim 1 , wherein an impurity concentration in the compound semiconductor region is set such that a potential barrier corresponding to a bandgap of the compound semiconductor region becomes greater than a potential barrier corresponding to a Schottky junction between the gate electrode of the second field effect transistor and the upper compound semiconductor layer.
10. The semiconductor device according to claim 1 , wherein the upper compound semiconductor layer is a first conductivity type layer and the compound semiconductor region is a second conductivity type region.
11. The semiconductor device according to claim 1 , wherein the upper compound semiconductor layer is a P-type layer and the compound semiconductor region is a N-type region.
12. The semiconductor device according to claim 9 , wherein the upper compound semiconductor layer is a first conductivity type layer and the compound semiconductor region is a second conductivity type region.
13. The semiconductor device according to claim 9 , wherein the upper compound semiconductor layer is a P-type layer and the compound semiconductor region is a N-type region.
14. The semiconductor device according to claim 3 , wherein an impurity concentration in the compound semiconductor region is greater than an impurity concentration in the electron supply layer.
15. The semiconductor device according to claim 1 , wherein a potential barrier corresponding to a bandgap of the compound semiconductor region is greater than a potential barrier corresponding to a Schottky junction between the gate electrode of the second field effect transistor and the upper compound semiconductor layer.