IP Library Granted Patent US 8,193,048
Granted Patent B2
US 8,193,048 · App. 12/061,367 · Granted Jun 5, 2012

Semiconductor device and method of manufacturing a semiconductor device

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Quick Facts
Patent No.
US 8,193,048
App. No.
12/061,367
Granted
Jun 5, 2012
Kind
B2
Abstract

A semiconductor device formed in a semiconductor substrate wherein the semiconductor substrate has a trench for isolating elements from each other, the trench has unevenness at the bottom thereof, and an insulator is buried in the trench.

Claims (34)

1. A method of manufacturing a semiconductor device comprising:

forming a mask pattern over a semiconductor substrate;

forming a trench having first unevenness in the semiconductor substrate by etching using the mask pattern;

burying an insulator in the trench;

forming a first well having a first conductivity type in the semiconductor substrate,

forming a first transistor in the first well,

forming a second well having a second conductivity type different from the first conductivity type in the semiconductor substrate,

forming a second transistor in the second well,

wherein a bottom of the trench includes a plurality of convex portions extending from the bottom of the trench toward a top of the trench

wherein the trench is located between the first well and the second well,

wherein the first unevenness includes a plurality of projections having a different height downward.

2. The method according to claim 1 , wherein a first difference in height of the first unevenness is greater than a second difference in height of second unevenness formed in a side wall of the trench.

3. The method according to claim 2 , wherein the first difference in height is 30% or less of a depth of the trench.

4. The method according to claim 3 , wherein the first difference in height is 4 nm or more.

5. The method according to claim 2 , wherein the etching is performed using a mixed gas containing chlorine gas and oxygen gas.

6. The method according to claim 5 , wherein the mixed gas further contains a nitrogen gas or a rare gas.

7. The method according to claim 2 , further comprising forming a thermal oxide film over the side wall of the trench before burying the insulator in the trench.

8. The method according to claim 7 , wherein a thickness of the thermal oxide film is less than the first difference in height.

9. The method according to claim 7 , wherein the second difference in height is a half or less of a thickness of the thermal oxide film.

10. The method according to claim 1 , wherein the etching to form the trench is performed using a mixed gas containing chlorine gas, oxygen gas and nitrogen gas.

11. The method according to claim 1 , wherein the trench has a taper angle with respect to a surface of the semiconductor substrate and the taper angle is adjusted by controlling a flow rate of nitrogen in an etching gas.

12. The method according to claim 1 , wherein the trench has a taper angle with respect to a surface of the semiconductor substrate and the taper angle is 80.degree. to 90.degree.

13. A method of manufacturing a semiconductor device comprising:

forming a mask pattern over a semiconductor substrate;

forming a trench having first unevenness in the semiconductor substrate by etching using the mask pattern, the trench having a taper angle with respect to a surface of the semiconductor substrate;

burying an insulator in the trench;

forming a first well having a first conductivity type in the semiconductor substrate,

forming a first transistor in the first well,

forming a second well having a second conductivity type different from the first conductivity type in the semiconductor substrate,

forming a second transistor in the second well,

wherein a bottom of the trench includes a plurality of convex portions extending from the bottom of the trench toward a top of the trench

wherein the trench is located between the first well and the second well,

wherein the taper angle is adjusted by controlling a flow rate of nitrogen in an etching gas.

14. The method according to claim 13 , wherein the first unevenness includes a plurality of projections having a different height downward.

Assignments (4)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 21, 2008
From: MIYAMOTO, MASATO; TERAHARA, MASANORI
To: FUJITSU LIMITED
Reel/Frame 020978/0736 →