Integrated RC oscillator with high frequency stability, notably for an integrated switched-mode power supply
An integrated oscillator ( 10 ), for an integrated circuit, comprises i) first (CI 1 ) and second (CI 2 ) compensated inverters mounted in series and each comprising first (PI 11 ;PI 21 ) and second (PI 12 ;PI 22 ) plain inverters mounted in parallel and comprising transistors having channel lengths respectively shorter and longer than an optimal channel length, the first compensated inverter (CI 1 ) having input and output terminals respectively connected to first (N 1 ) and second (N 2 ) nodes and the second compensated inverter (CI 2 ) having input and output terminals respectively connected to the second node (N 2 ) and to a third node (N 3 ), ii) a resistor (R) having a chosen resistance value and comprising first and second terminals connected respectively to the first (N 1 ) and second (N 2 ) nodes, and iii) a capacitor (C) comprising first and second terminals connected respectively to the first (N 1 ) and third (N 3 ) nodes, and having a chosen capacitance value to charge and discharge oneself in order to periodically deliver a clock signal at the desired oscillation frequency.
1. An integrated oscillator, comprising:
a first compensated inverter having input and output terminals respectively connected to first and second nodes, the first compensated inverter including a first plain inverter and a second plain inverter coupled in parallel to each other, the first plain inverter having a channel length that is shorter than a channel length of the second plain inverter;
a second compensated inverter having input and output terminals respectively connected to said second node and to a third node, the second compensated inverter including a third plain inverter and a fourth plain inverter coupled in parallel to each other, the third plain inverter having a channel length that is shorter than a channel length of the fourth plain inverter;
a resistor having a resistance value and comprising first and second terminals connected respectively to said first and second nodes; and
a capacitor comprising first and second terminals connected respectively to said first and third nodes, and having a capacitance value, the inverters, resistor, and capacitor being configured to deliver a clock signal at the third node at an oscillation frequency.
2. The integrated oscillator according to claim 1 , wherein the channel lengths of the first and third plain inverters are shorter than a temperature-stable channel length, and the channel lengths of the second and fourth plain inverters are longer than a temperature-stable channel length, the temperature-stable channel length being a channel length at which the plain inverters would have an oscillation frequency that substantially would not change with temperature.
3. The integrated oscillator according to claim 2 , wherein channel length differences between the channel lengths of said plain inverters and said temperature-stable channel length are such to maintain substantially constant the oscillation frequency of the clock signal over a desired temperature range.
4. The integrated oscillator according to claim 3 , wherein the channel length differences are chosen such that said oscillation frequency of the clock signal remains constant over a process spread.
5. The integrated oscillator according to claim 1 , wherein:
each plain inverter comprises a pMOS transistor and a nMOS transistor, each transistor having a gate, a source and a drain;
the gates of the transistors of the first compensated inverter are connected to said first node;
the gates of the transistors of the second compensated inverter are connected to said second node;
the sources of the pMOS transistors of the first and second compensated inverters are connected to a supply node;
the drains of the transistors of the first compensated inverters are connected to said second node;
the drains of the second compensated inverters are connected to said third node; and
the sources of the nMOS transistors of the first and second compensated inverters are connected to a ground.
6. An integrated switched-mode power supply, comprising:
a DC-DC converter comprising a first input configured to receive an input DC voltage, a second input, and an output configured to deliver an output DC voltage; and
an integrated oscillator configured to deliver a clock signal and an oscillation frequency on an oscillator output that is coupled to the second input of the DC-DC converter, the oscillator including:
a first compensated inverter having input and output terminals respectively connected to first and second nodes, the first compensated inverter including a first plain inverter and a second plain inverter coupled in parallel to each other, the first plain inverter having a channel length that is shorter than a channel length of the second plain inverter;
a second compensated inverter having input and output terminals respectively connected to said second node and to a third node coupled to the oscillator output, the second compensated inverter including a third plain inverter and a fourth plain inverter coupled in parallel to each other, the third plain inverter having a channel length that is shorter than a channel length of the fourth plain inverter;
a resistor having a resistance value and comprising first and second terminals connected respectively to said first and second nodes; and
a capacitor comprising first and second terminals connected respectively to said first and third nodes, and having a capacitance value.
7. An electronic device, comprising:
a battery arranged to deliver an input DC voltage;
an integrated switched-mode power supply arranged to convert said input DC voltage into an output DC voltage, and
a circuit configured to be powered by said output DC voltage, said integrated switched-mode power supply includes:
a DC-DC converter comprising a first input configured to receive the input DC voltage, a second input, and an output configured to deliver the output DC voltage; and
an integrated oscillator configured to deliver a clock signal and an oscillation frequency on an oscillator output that is coupled to the second input of the DC-DC converter, the oscillator including:
a first compensated inverter having input and output terminals respectively connected to first and second nodes, the first compensated inverter including a first plain inverter and a second plain inverter coupled in parallel to each other, the first plain inverter having a channel length that is shorter than a channel length of the second plain inverter;
a second compensated inverter having input and output terminals respectively connected to said second node and to a third node coupled to the oscillator output, the second compensated inverter including a third plain inverter and a fourth plain inverter coupled in parallel to each other, the third plain inverter having a channel length that is shorter than a channel length of the fourth plain inverter;
a resistor having a resistance value and comprising first and second terminals connected respectively to said first and second nodes; and
a capacitor comprising first and second terminals connected respectively to said first and third nodes, and having a capacitance value.
8. Use of the integrated oscillator according to claim 1 to deliver highly stable clock signals.
9. The integrated switched-mode power supply according to claim 6 , wherein the channel lengths of the first and third plain inverters are shorter than a temperature-stable channel length, and the channel lengths of the second and fourth plain inverters are longer than a temperature-stable channel length, the temperature-stable channel length being a channel length at which the plain inverters would have an oscillation frequency that substantially would not change with temperature.
10. The integrated switched-mode power supply according to claim 9 , wherein channel length differences between the channel lengths of said plain inverters and said temperature-stable channel length are such to maintain substantially constant the oscillation frequency of the clock signal over a desired temperature range.
11. The integrated switched-mode power supply according to claim 10 , wherein the channel length differences are chosen such that said oscillation frequency of the clock signal remains constant over a process spread.
12. The integrated switched-mode power supply according to claim 6 , wherein:
each plain inverter comprises a pMOS transistor and a nMOS transistor, each transistor having a gate, a source and a drain;
the gates of the transistors of the first compensated inverter are connected to said first node;
the gates of the transistors of the second compensated inverter are connected to said second node;
the sources of the pMOS transistors of the first and second compensated inverters are connected to a supply node;
the drains of the transistors of the first compensated inverters are connected to said second node;
the drains of the second compensated inverters are connected to said third node; and
the sources of the nMOS transistors of the first and second compensated inverters are connected to a ground.
13. The electronic device according to claim 7 , wherein the channel lengths of the first and third plain inverters are shorter than a temperature-stable channel length, and the channel lengths of the second and fourth plain inverters are longer than a temperature-stable channel length, the temperature-stable channel length being a channel length at which the plain inverters would have an oscillation frequency that substantially would not change with temperature.
14. The electronic device according to claim 13 , wherein channel length differences between the channel lengths of said plain inverters and said temperature-stable channel length are such to maintain substantially constant the oscillation frequency of the clock signal over a desired temperature range.
15. The electronic device according to claim 14 , wherein the channel length differences are chosen such that said oscillation frequency of the clock signal remains constant over a process spread.
16. The electronic device according to claim 7 , wherein:
each plain inverter comprises a pMOS transistor and a nMOS transistor, each transistor having a gate, a source and a drain;
the gates of the transistors of the first compensated inverter are connected to said first node;
the gates of the transistors of the second compensated inverter are connected to said second node;
the sources of the pMOS transistors of the first and second compensated inverters are connected to a supply node;
the drains of the transistors of the first compensated inverters are connected to said second node;
the drains of the second compensated inverters are connected to said third node; and
the sources of the nMOS transistors of the first and second compensated inverters are connected to a ground.