Logic modules for semiconductor integrated circuits
View Patent ↗A logic module ( 400 ) that is capable of implementing data-path and random logic (command Z in block 42 ) uses control logic for selectively coupling one or more of the input terminals ( 10, 12, 14, 16, 18, 40 ) to the at least one output terminal ( 20 ). The control logic comprises a plurality of logic elements ( 26, 28, 30, 32 ) arranged to generate a first set of two-input logic functions (f, (a, b)) and a programmable inverter ( 36 ) arranged to generate a second set of two-input logic functions, the second set of two-input logic functions being the complement functions of the first set of two-input logic functions. SRAM memory cells (4 bit memory batch ( 38 )) may be used for configuration purposes, realizing a compact logic module or block that is also re-programmable.
1. A logic module comprising:
a plurality of input terminals;
at least one output terminal; and
control logic between the input terminals and the at least one output terminal, the control logic comprising a plurality of multiplexer logic elements programmable to generate each of a first set of at least two-input logic functions and an inverter programmable to produce from the first set, a second set of at least two-input logic functions which are the complement functions of the first set of at least two-input logic functions.
2. A logic module according to claim 1 , wherein the first and second set of at least two-input logic functions comprise all possible two-input logic functions.
3. A logic module according to claim 1 , wherein the plurality of multiplexer logic elements comprise a plurality of 2:1 multiplexers.
4. A logic module according to claim 2 wherein the programmable inverter is a XOR logic gate.
5. A logic module according to claim 1 , wherein the programmable inverter is a multiplexer, the multiplexer having its input signals connected to a function and the complement of the function and being arranged to output one of the input signals in response to a selection signal.
6. A logic module according to claim 1 , wherein the control logic is further arranged to complete 1-bit addition.
7. A logic module according to claim 1 , wherein the logic module is re-programmable.
8. The logic module according to claim 1 wherein the plurality of input terminals comprises:
first operand, second operand, first configuration and second configuration terminals;
the control logic comprise;
first to fourth 2:1 multiplexers; and
a two-input AND logic gate;
the inverter comprises a two-input XOR logic gate;
the logic module further comprising a memory latch;
wherein;
the memory latch is connected to the first configuration terminal;
the two-input AND logic gate has one of its inputs connected to the first operand terminal and the other of its inputs connected to the second configuration terminal;
the first 2:1 multiplexer has its two signal terminals respectively connected to the output of the two-input AND logic gate and the complement of the output of the two-input AND logic gate, and its selection terminal connected to a first bit of the memory latch, the second signal terminal of the first 2:1 multiplexer also being connected to the second signal terminal of the second 2:1 multiplexer;
the second 2:1 multiplexer has its first signal terminal connected to a ground signal, and its selection terminal connected to a second bit of the memory latch;
the third 2:1 multiplexer has its two signal terminals respectively connected to the second operand terminal and the complement of the second operand terminal, and its selection terminal connected to a third bit of the memory latch;
the fourth 2:1 multiplexer has its two signal terminals respectively connected to the signals selected by the first and second 2:1 multiplexers, and its selection terminal connected to the signal selected by the third 2:1 multiplexer;
the two-input XOR logic gate has one of its inputs connected to the signal selected by the fourth 2:1 multiplexer and the other of its inputs connected to a fourth bit of the memory latch; and
the output terminal receives an output signal of the XOR logic gate.
9. A logic module according to claim 8 , further comprising;
a carry-in terminal;
a fifth 2:1 multiplexer; and
a second output terminal, wherein:
the two-input XOR logic gate has one of its inputs connected to the signal selected by the fourth 2:1 multiplexer and the other of its inputs connected to the carry-in terminal;
the fifth 2:1 multiplexer has its two signal terminals respectively connected to the output of the two-input AND logic gate and the carry-in terminal, and its selection terminal connected to the signal selected by the fourth multiplexer; and
the second output terminal receives a signal selected by the fifth 2:1 multiplexer.
10. A logic module according to claim 9 , further comprising a third configuration terminal and a sixth 2:1 multiplexer, wherein:
the sixth 2:1 multiplexer has its two signal terminals respectively connected to the carry-in terminal and a fourth bit of the memory latch, and its selection terminal connected to the third configuration terminal; and
the two-input XOR logic gate has one of its inputs connected to the signal selected by the fourth 2:1 multiplexer and the other of its inputs connected to the signal selected by the sixth 2:1 multiplexer.
11. A semiconductor integrated circuit comprising at least one logic module according to claim 1 .
12. A method of generating at least two-input logic functions from control logic, the control logic comprising a plurality of multiplexer logic elements and an inverter, the method comprising the steps of:
programming the plurality of multiplexer logic elements to generate each of a first set of at least two-input logic functions; and
programming the inverter to produce from the first set, a second set of at least two-input logic functions which are the complement functions of the first set of at least two-input logic functions;
wherein said programming comprises writing data signals to a memory of the control logic and applying the data signals from the memory to the plurality of multiplexer logic elements and to the inverter.
13. A logic module according to claim 1 , wherein the logic module comprises a memory latch connected to the plurality of multiplexer logic elements and to the inverter, said plurality of multiplexer logic elements and said inverter being re-programmable in response to said memory latch.
14. A logic module comprising:
a plurality of input terminals;
at least one output terminal; and
control logic between the input terminals and the at least one output terminal, the control logic comprising a plurality of multiplexer logic elements programmable to generate each of a first set of at least two-input logic functions and an inverter programmable to produce from the first set, a second set of at least two-input logic functions which are the complement functions of the first set of at least two-input logic functions;
wherein the control logic comprises a re-programmable memory connected to the plurality of multiplexer logic elements and to the inverter, said plurality of multiplexer logic elements and said inverter being re-programmable in response to said re-programmable memory.