Architecture for device having cantilever electrode
In one embodiment, a non-volatile memory bitcell includes a program electrode, an erase electrode, a cantilever electrode connected to a bi-stable cantilever positioned between the program electrode and the erase electrode, and switching means connected to the program electrode arranged to apply a voltage potential onto the program electrode, or to detect or to prevent the flow of current from the cantilever to the program electrode. The switching means may comprise a switch having a first node, a second node, and a control node, wherein voltage is applied to the control node to activate the switch to provide a connection between the first node and the second node. The switching means may comprise a pass-gate. The switching means may comprise an NMOS transistor. The switching means may comprise a PMOS transistor. The switching means may comprise a MEMS switch.
1. A device, comprising:
a first inter-metal dielectric layer having metallization structures formed therein;
a first electrode disposed over the metallization structures;
a second electrode disposed over the first electrode and coupled to the metallization structures through connecting vias;
an insulating layer disposed on the second electrode; and
a cantilever electrode connected to a cantilever positioned between the second electrode and the first electrode within a cavity, wherein the insulating layer is disposed between the cantilever and the second electrode, wherein the cantilever is movable between the first electrode and the insulating layer, and wherein the second electrode borders the cavity on at least one side perpendicular to the insulating layer.
2. The device of claim 1 , further comprising an electrically insulated layer disposed on the cantilever.
3. The device of claim 1 , wherein the cavity is sealed and integrated into the back-end-of-line of a CMOS process.
4. The device of claim 1 , further comprising a second inter-metal dielectric layer disposed over the second electrode and sealing the cavity.
5. The device of claim 4 , further comprising a passivation layer disposed over the second inter-metal dielectric layer.
6. The device of claim 5 , wherein the passivation layer comprises a material selected from the group consisting of silicon dioxide and silicon nitride.