Semiconductor device
View Patent ↗In a semiconductor device including multiple unit cells arranged in an array, transistors are affected by a stress from an STI at different degrees depending on the position in the array. As a result, a variation occurs in transistor characteristic. In a semiconductor device according to the present invention, each of predetermined transistors in outermost unit blocks in the array has a transistor size according to the stress from the STI.
1. A semiconductor integrated circuit, comprising:
an array of a plurality of unit cells, each of said unit cells having a same size; and
a device isolation surrounding the array,
wherein one of said unit cells in a vicinity of the device isolation has a transistor of a different physical characteristic and substantially a same electrical characteristic as compared with another transistor in another of said unit cells provided away from the device isolation, and
wherein said one transistor has a smaller channel width than that of said another transistor.
2. A semiconductor integrated circuit according to claim 1 , wherein the physical characteristic is one of a gate width and a gate length of the transistor.
3. A semiconductor integrated circuit according to claim 1 , wherein the unit cell includes a flip-flop circuit.
4. A semiconductor integrated circuit according to claim 1 , wherein the unit cell includes an SRAM cell.
5. A semiconductor integrated circuit according to claim 1 , wherein each of the unit cells in the array is electrically activated in response to a respective control signal.
6. A semiconductor integrated circuit according to claim 1 , wherein the one transistor comprises an N-type MOS transistor and said another transistor comprises another N-type MOS transistor, said one and another transistors having corresponding functions in respective unit cells, said one transistor having a larger channel width than said another N-type MOS transistor.
7. A semiconductor integrated circuit according to claim 1 , wherein the one transistor comprises a N-type MOS transistor and said another transistor comprises another N-type MOS transistor, said one and another transistors having corresponding functions in respective unit cells, said one transistor having a shorter channel length than said another N-type MOS transistor.
8. A semiconductor integrated circuit according to claim 1 , wherein the one transistor comprises a P-type MOS transistor and said another transistor comprises another P-type MOS transistor, said one and another transistors having corresponding functions in respective unit cells, said one transistor having a longer channel length than said another P-type MOS transistor.
9. A semiconductor integrated circuit, comprising:
an array of a plurality of unit cells, each of said unit cells having a same size; and
a device isolation surrounding the array,
wherein one of said unit cells in a vicinity of the device isolation has a transistor of a different physical characteristic and substantially a same electrical characteristic as compared with another transistor in another of said unit cells provided away from the device isolation, and
wherein the one transistor comprises a P-type MOS transistor and said another transistor comprises another P-type MOS transistor, said one and another transistors having corresponding functions in respective unit cells, said one transistor having a smaller channel width than that of said another P-type MOS transistor.
10. A semiconductor integrated circuit according to claim 9 , wherein said one unit cell is located in the vicinity of the device isolation and away from a corner of the device isolation,
wherein said circuit includes yet another unit cell located in a vicinity of said corner and having yet another transistor, and
wherein the P-type MOS transistor has a smaller channel width than that of the one transistor.
11. A semiconductor integrated circuit, comprising:
an array of a plurality of unit cells, each of said unit cells having a same size; and
a device isolation surrounding the array,
wherein one of said unit cells in a vicinity of the device isolation has a transistor of a different physical characteristic and substantially a same electrical characteristic as compared with another transistor in another of said unit cells provided away from the device isolation,
wherein the one transistor comprises an N-type MOS transistor and said another transistor comprises another N-type MOS transistor, said one and another transistors having corresponding functions in respective unit cells, said one transistor having a larger channel width than said another N-type MOS transistor,
wherein said one unit cell is located in the vicinity of the device isolation and away from a corner of the device isolation,
wherein said circuit includes yet another unit cell located in a vicinity of said corner and having yet another transistor, and
wherein the N-type MOS transistor has a larger channel width than that of the one transistor.
12. A semiconductor integrated circuit, comprising:
an array of a plurality of unit cells, each of said unit cells having a same size; and
a device isolation surrounding the array,
wherein one of said unit cells in a vicinity of the device isolation has a transistor of a different physical characteristic and substantially a same electrical characteristic as compared with another transistor in another of said unit cells provided away from the device isolation,
wherein the one transistor comprises a N-type MOS transistor and said another transistor comprises another N-type MOS transistor, said one and another transistors having corresponding functions in respective unit cells, said one transistor having a shorter channel length than said another N-type MOS transistor,
wherein said one unit cell is located in the vicinity of the device isolation and away from a corner of the device isolation,
wherein said circuit includes yet another unit cell located in a vicinity of said corner and having yet another transistor, and
wherein the N-type MOS transistor has a shorter channel length than that of the one transistor.
13. A semiconductor integrated circuit, comprising:
an array of a plurality of unit cells, each of said unit cells having a same size; and
a device isolation surrounding the array,
wherein one of said unit cells in a vicinity of the device isolation on has a transistor of a different physical characteristic and substantially a same electrical characteristic as compared with another transistor in another of said unit cells provided away from the device isolation,
wherein the one transistor comprises a P-type MOS transistor and said another transistor comprises another P-type MOS transistor, said one and another transistors having corresponding functions in respective unit cells, said one transistor having a longer channel length than said another P-type MOS transistor,
wherein said one unit cell is located in the vicinity of the device isolation and away from a corner of the device isolation,
wherein said circuit includes yet another unit cell located in a vicinity of said corner and having yet another transistor, and
wherein the P-type MOS transistor has a longer channel length than that of the one transistor.
14. A semiconductor integrated circuit, comprising:
an array of a plurality of unit cells; and
a device isolation surrounding the array,
wherein one of said unit cells in a vicinity of the device isolation has a transistor of a different physical characteristic and substantially the same electrical characteristic as compared with another transistor in another of said unit cells provided away from the device isolation, and
wherein the one transistor comprises a P-type MOS transistor and said another transistor comprises another P-type MOS transistor, said one and another transistors having corresponding functions in respective unit cells, said one transistor having a smaller channel width than that of said another P-type MOS transistor.
15. A semiconductor integrated circuit, comprising:
an array including a plurality of unit cells, each of said unit cells having a same size, said unit cell including one of a P-type and an N-type MOS transistor, and an STI adjacent to the transistor; and
a peripheral area comprising of an STI surrounding the array,
wherein a size of a predetermined transistor in a unit cell in a vicinity of the peripheral area is set according to a stress from the peripheral area to allow the predetermined transistor to have an equivalent characteristic to that of a transistor having the same function as that of the predetermined transistor in a unit cell other than the unit cell in the vicinity of the peripheral area, and
wherein said predetermined transistor has a smaller channel width than that of said transistor.
16. A semiconductor integrated circuit comprising:
an array including a plurality of unit cells, each of said unit cells having a same size, said unit cell including one of a P-type and N-type MOS transistor, and an STI adjacent to the transistor; and
a peripheral area comprising of an STI surrounding the array,
wherein a size of a predetermined transistor in a unit cell in a vicinity of the peripheral area is set according to a stress from the peripheral area to allow the predetermined transistor to have an equivalent characteristic to that of a transistor having the same function as that of the predetermined transistor in a unit cell other than the unit cell in the vicinity of the peripheral area, and
wherein the predetermined transistor comprises a P-type MOS transistor and said transistor comprises another P-type MOS transistor, said predetermined transistor and said transistor having corresponding functions in respective unit cells, said predetermined transistor having a smaller channel width than that of said another P-type MOS transistor.