Semiconductor circuit including electrostatic discharge circuit having protection element and trigger transistor
View Patent ↗A semiconductor circuit includes, a first pad for a first power source, a second pad for a second power source, a third pad for an input/output signal, a protection element arranged between the third pad and the second pad; and a transistor functioning as a trigger element for use in flowing a trigger current to the protection element. The transistor includes a gate and a backgate being connected to the first pad and is connected to the protection element such that a source potential of the transistor becomes lower than a potential of the third pad, based on a voltage drop caused by the protection element, when potentials of the first pad and the third pad are kept at a power supply voltage level.
1. A semiconductor circuit, comprising:
a first pad for a first power source;
a second pad for a second power source;
a third pad for an input/output signal;
a silicon controlled rectifier (SCR) arranged between the third pad and the second pad; and
a transistor functioning as a trigger element to flow a trigger current to a gate of the SCR, the transistor including a gate and a backgate being connected to the first pad,
wherein an anode of the SCR is connected to the third pad,
wherein a cathode of the SCR is connected to the second pad,
wherein the gate of the SCR is connected to the source of the transistor,
wherein the SCR comprises:
a member of a P-type substrate or a P-well;
a first P + region formed in the member and connected to the second pad;
a first N + region formed in the member and connected to the second pad;
an N-well formed in the P- type substrate or adjacent to the P-well;
a second P + region formed in the N-well and connected to the third pad; and
a second N + region formed in the N-well and connected to the source of the transistor, and
wherein the first N + region and the second P + region are formed adjacent to each other and are formed between the first P + region and the second N + region.
2. The semiconductor circuit as claimed in claim 1 , wherein said transistor comprises a PMOS transistor, said first power source comprises VDD, and said second power source comprises VSS.
3. The semiconductor circuit as claimed in claim 1 , wherein the first N + region is disposed adjacent to the second P + region.
4. The semiconductor circuit as claimed in claim 1 , wherein the second P + region is disposed adjacent to the second N + region.
5. The semiconductor circuit as claimed in claim 1 , wherein the SCR further comprises:
a field oxide film that abuts the second P + region and the first N + region.
6. The semiconductor circuit as claimed in claim 1 , wherein the first P + region, the first N+ region, the second P + region, and the second N + region are disposed in order in the SCR.
7. The semiconductor circuit as claimed in claim 1 , wherein the first N + region comprises the cathode of the SCR.
8. The semiconductor circuit as claimed in claim 1 , wherein the second P + region comprises the anode of the SCR.
9. The semiconductor circuit as claimed in claim 1 , wherein the second N + region comprises the gate of the SCR.
10. The semiconductor circuit as claimed in claim 1 , wherein the SCR further comprises:
an NPN transistor; and
a resistor disposed in one of the P-type substrate and the P-well, said resistor applying a bias to the NPN transistor.
11. The semiconductor circuit as claimed in claim 10 , wherein the resistor is electrically connected to the first P + region.
12. The semiconductor circuit as claimed in claim 11 , wherein the SCR further comprises:
a PNP transistor; and
a resistor disposed in the N-well, said resistor electrically connecting the second N + region to a base of the PNP transistor.
13. The semiconductor circuit as claimed in claim 1 , wherein the SCR further comprises:
a PNP transistor; and
a resistor disposed in the N-well, said resistor electrically connecting the gate of the SCR to a base of the PNP transistor.