Dither circuit and analog digital converter having dither circuit
View Patent ↗According to one aspect of the present invention, there is provided a dither circuit including a dither generating circuit generating a plurality of complementary signal pairs, and a dither input circuit generating a plurality of dither signals from the plurality of complementary signal pairs to add the generated dither signals to an analog input signal, in which the plurality of complementary signal pairs have different frequencies with each other, the dither input circuit includes capacitors provided for each of the plurality of complementary signal pairs and a plurality of switch pairs including first and second switches having one terminals connected to each one terminal of the capacitors, and the other terminals of the capacitors are connected to an adding point to the analog input signal, the first switch supplies ones of the complementary signal pairs to one terminals of the capacitors when a clock signal is in effective state, and the second switch supplies the others of the complementary signal pairs to one terminals of the capacitors when an inverting clock signal of the clock signal is in effective state.
1. A dither circuit comprising:
a dither generating circuit generating a plurality of complementary signal pairs; and
a dither input circuit generating a plurality of pairs of dither signals from the plurality of complementary signal pairs to add the generated dither signals to an analog input signal, wherein
the plurality of complementary signal pairs have different frequencies with each other,
the dither input circuit includes capacitors provided for each of the plurality of complementary signal pairs and a plurality of switch pairs including first and second switches having one terminals connected to each one terminal of the capacitors, and
the other terminals of the capacitors are connected to an adding point to the analog input signal, the first switch supplies ones of the complementary signal pairs to one terminals of the capacitors when a clock signal is in effective state, and the second switch supplies the others of the complementary signal pairs to one terminals of the capacitors when an inverting clock signal of the clock signal is in effective state.
2. The dither circuit according to claim 1 , wherein each capacitor has different capacitance value with each other.
3. The dither circuit according to claim 1 , wherein each signal of the complementary signal pairs has amplitude between power source potential and ground potential.
4. The dither circuit according to claim 1 , wherein the dither generating circuit includes a frequency divider generating the complementary signal pairs having a plurality of frequencies of ½″ (n is an integer of one or more than one) of the clock signal.
5. The dither circuit according to claim 4 comprising a selector selecting complementary signal pairs generated by the dither generating circuit to supply the selected complementary signal pairs to the dither input circuit.
6. The dither circuit according to claim 1 , wherein the dither generating circuit comprises:
a plurality of D-type flip-flops connected in a sequential manner, wherein a Q-output of one of the D-type flip-flops is connected to a D-input of the one of the D-type flip-flops and to a Clock input of a succeeding one of the D-type flip-flops that are connected in the sequential manner.
7. An analog digital converter comprising:
a dither circuit including;
a dither generating circuit generating a plurality of complementary signal pairs; and
a dither input circuit generating a plurality of pairs of dither signals from the plurality of complementary signal pairs to add the generated dither signals to an analog input signal, wherein
the plurality of complementary signal pairs have different frequencies with each other,
the dither input circuit includes capacitors provided for each of the plurality of complementary signal pairs and a plurality of switch pairs including first and second switches having one terminals connected to each one terminal of the capacitors, and
the other terminals of the capacitors are connected to an adding point to the analog input signal, the first switch supplies ones of the complementary signal pairs to one terminals of the capacitors when a clock signal is in effective state, and the second switch supplies the others of the complementary signal pairs to one terminals of the capacitors when an inverting clock signal of the clock signal is in effective state.
8. The analog digital converter according to claim 7 , wherein each capacitor has different capacitance value with each other.
9. The analog digital converter according to claim 7 , wherein each signal of the complementary signal pairs has amplitude between power source potential and ground potential.
10. The analog digital converter according to claim 7 , wherein the dither generating circuit includes a frequency divider generating the complementary signal pairs having a plurality of frequencies of ½″ (n is an integer of one or more than one) of the clock signal.
11. The analog digital converter according to claim 10 comprising a selector selecting complementary signal pairs generated by the dither generating circuit to supply the selected complementary signal pairs to the dither input circuit.
12. The analog digital converter according to claim 7 , wherein the analog digital converter is a delta sigma type analog digital converter.
13. The analog digital converter according to claim 12 comprising a switched capacitor type integrator, wherein the other ends of each capacitor of the dither input circuit is connected to a connecting point of a capacitor for analog signal input and an integral capacitor.
14. The analog digital converter according to claim 13 , wherein the capacitance values of each capacitor of the dither input circuit are less than 1/10 of the capacitance value of the capacitor for analog signal input.
15. The analog digital converter according to claim 6 , wherein the dither generating circuit comprises:
a plurality of D-type flip-flops connected in a sequential manner, wherein a Q-output of one of the D-type flip-flops is connected to a D-input of the one of the D-type flip-flops and to a Clock input of a succeeding one of the D-type flip-flops that are connected in the sequential manner.