IP Library Granted Patent US 7,491,640
Granted Patent B2
US 7,491,640 · App. 12/073,274 · Granted Feb 17, 2009

Method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 7,491,640
App. No.
12/073,274
Granted
Feb 17, 2009
Kind
B2
Abstract

In a dual damascene process to form a fine interconnection structure, a semiconductor manufacturing method includes: forming a first film to be etched on an insulating layer on a semiconductor substrate; forming a first mask film with an opening on the first film; forming a second film to be etched on the first mask film, burying the opening; forming a second mask film on the second film to be etched; forming an interconnection pattern in the second mask film in the upper portion of the opening; forming an interconnection pattern by etching the second film using the second mask film, forming a via pattern by etching the first film to be etched using the first mask film; and forming a via hole and an interconnection trench in the upper portion of the via hole in the insulating layer by selectively etching the insulating layer using the interconnection and via patterns.

Claims (11)

1. A method of fabricating a semiconductor device, comprising:

forming a first film with an opening on an insulating layer formed on a semiconductor substrate;

forming a second film on said first film in such a way that said opening is buried;

forming a trench pattern on said second film so that said trench pattern overlaps with said opening portion;

forming a via pattern by etching said first film using said trench pattern to expose said insulating layer; and

forming a via hole and an interconnect trench in the upper portion of said via hole in said insulating layer employing said via pattern and said trench pattern,

wherein a width of said via hole depends on a part of said trench pattern and said opening having a larger width than said width of the via hole.

2. The method of claim 1 , wherein one side of said trench pattern is between said opening.

3. The method of claim 1 , wherein said first film is a multilayer.

4. The method of claim 1 , wherein said second film is a multilayer.

5. The method of claim 1 , wherein said insulating layer is a multilayer.

Assignments (4)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Nov 2, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025235/0497 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2010
From: RODENBURG, DIRK
To: RELEVANT SOFTWARE INC.
Reel/Frame 023965/0402 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2008
From: NAGASE, MASATOSHI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 020650/0058 →