Clock generator circuit, clock selector circuit, and semiconductor integrated circuit
A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector.
1. A clock generator circuit comprising:
a phase synchronizing circuit outputting a second clock synchronized with a first clock;
a selector outputting either the first clock or the second clock as an output clock according to a switching signal;
a selector signal generator circuit outputting the switching signal for the selector to output the first clock instead of the second clock when an abnormal waveform pulse is detected in the second clock; and
a delay circuit delaying the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock according to the switching signal before the abnormal waveform pulse is input to the selector.
2. The clock generator circuit according to claim 1 ,
wherein the selector signal generator circuit includes:
an abnormal pulse detector circuit detecting the abnormal waveform pulse and outputting an abnormal detection signal when finding the abnormal waveform pulse; and
a timing control circuit outputting the abnormal detection signal, synchronized with the first clock, to the selector as the switching signal.
3. The clock generator circuit according to claim 2 ,
wherein the abnormal pulse detector circuit includes:
a first level detector circuit judging whether signal levels of the second clock at multiple time points are at a first level; and
a second level detector circuit judging whether signal levels of the second clock at multiple time points are at a second level.
4. The clock generator circuit according to claim 1 , wherein an amount of delay in the delay circuit is set based on a processing time for the selector signal generator circuit and the selector.
5. The clock generator circuit according to claim 4 , wherein the delay circuit comprises multiple serially connected buffers.
6. The clock generator circuit according to claim 1 , further comprising:
a stop signal generator circuit outputting a system stop signal in order to stop function circuits operated by the output clock, based on detection of an abnormal waveform pulse in the first clock and detection of the abnormal waveform pulse in the second clock.
7. The clock generator circuit according to claim 6 ,
wherein the abnormal pulse detector circuit comprises a first abnormal pulse detector circuit, and
wherein the stop signal generator circuit includes:
a second abnormal pulse detector circuit outputting an abnormal detection signal when detecting the abnormal waveform pulse in the first clock; and
a decision circuit outputting the system stop signal based on the abnormal detection signals from the second abnormal pulse detector circuit and the first abnormal pulse detector circuit.
8. The clock generator circuit,
a phase synchronizing circuit outputting a second clock synchronized with a first clock;
a selector outputting either the first clock or the second clock as an output clock according to a switching signal; and
a selector signal generator circuit outputting the switching signal for the selector to output the first clock instead of the second clock when an abnormal waveform pulse is detected in the second clock;
wherein the selector signal generator circuit includes:
an abnormal pulse detector circuit detecting the abnormal waveform pulse and outputting an abnormal detection signal when detecting the abnormal waveform pulse; and
a timing control circuit outputting the abnormal detection signal, synchronized with the first clock, to the selector as the switching signal.
9. The clock generator circuit according to claim 8 , wherein the timing control circuit comprises a flip-flop circuit.
10. A clock selector circuit comprising:
a selector outputting either a first clock or a second clock as an output clock based on a switching signal;
a selector signal generator circuit outputting the switching signal to the selector to output the first clock instead of the second clock when an abnormal waveform pulse is detected in the second clock input to the selector; and
a delay circuit delaying the second clock input to the selector in order to switch the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector.
11. The clock selector circuit according to claim 10 ,
wherein the selector signal generator circuit includes:
an abnormal pulse detector circuit outputting an abnormal detection signal when detecting the abnormal waveform pulse; and
a timing control circuit outputting the abnormal detection signal, synchronized with the first clock, to the selector as the switching signal.
12. The clock selector circuit according to claim 11 ,
wherein the abnormal pulse detector circuit includes:
a first level detector circuit judging whether signal levels of the second clock at multiple time points are at a first level; and
a second level detector circuit judging whether signal levels of the second clock at multiple time points are in a second level.
13. The clock selector circuit according to claim 10 , wherein an amount of delay in the delay circuit is set based on a processing time for the selector signal generator circuit and the selector.
14. The clock selector circuit according to claim 13 , wherein the delay circuit comprises multiple serially connected buffers.