Semiconductor device
The invention provides a semiconductor apparatus capable of achieving a device having a snap-back resisting pressure of about 5 to 10 V by a self-aligning process. The semiconductor apparatus includes two or more sub-gates placed next to a main gate at a predetermined interval, and low concentration layers placed continuously from the ends of source/drain layers to near the end of the main gate, having a potential type same as that of the source/drain layers, and having an impurity concentration lower than that of the source/drain layers.
1 . A method of forming a MOS transistor, comprising:
forming a conductive film over a semiconductor substrate;
selectively removing said film to leave a continuous pattern of said film having a main gate portion, a sub-gate portion and a connection portion, said main gate portion and said sub-gate portion being adjacent to each other with a space therebetween where said film was removed;
forming a source/drain region on said substrate; and
forming an impurity diffusion region placed continuously from the end of said source/drain region to near the end of said main gate under said sub-gate, said impurity region having a conductivity type which is the same as that of said source/drain region and having an impurity concentration lower than that of said source/drain region.
2 . The method as claimed in claim 1 , wherein the source/drain region is formed using the conductive film as a mask.
3 . The method as claimed in claim 1 , wherein the sub-gate portion comprises sub-gates formed next to said main gate on both sides of said main gate.
4 . The method as claimed in claim 3 , wherein a number of said sub-gates next to said main gate on one side is different from the number of said sub-gates formed on the other side.
5 . The method as claimed in claim 1 , wherein said sub-gate is placed next to said main gate only on the drain side.
6 . The method as claimed in claim 5 , wherein said impurity diffusion region is formed only on the drain side.
7 . The method as claimed in claim 1 , wherein said impurity diffusion region is a lightly doped drain (LDD) region.
8 . The method as claimed in claim 1 , wherein said impurity diffusion region is a double diffused drain (DDD) layer.
9 . The method as claimed in claim 1 , wherein said impurity diffusion is an extension region.
10 . The method as claimed in claim 1 , further comprising a side wall formed between said main gate and said sub-gate not to link said main gate with said sub-gate.
11 . The method as claimed in claim 1 , further comprising a side wall formed between said main gate and said sub-gate to link said main gate with said sub-gate.
12 . The method as claimed in claim 1 , further comprising a second source/drain region formed in said impurity diffusion region and between said main gate and said sub-gate.
13 . The method as claimed in claim 12 , further comprising a silicide layer placed on the surface of said second source/drain region.
14 . The method as claimed in claim 1 , wherein said transistor is an NMOS type transistor or PMOS type transistor.
15 . The method as claimed in claim 14 , wherein said transistor is formed on a semiconductor device having transistors having mutually different breakdown resisting pressures.
16 . The method as claimed in claim 15 , wherein said substrate is a P type silicon substrate or N type silicon substrate.
17 . The method as claimed in claim 1 , wherein the impurity diffusion region is formed using the conductive film as a mask.
18 . A method of forming a MOS transistor, comprising:
forming a semiconductor substrate of a first conductivity type;
forming an element isolation region on said semiconductor substrate to define an element formation region;
forming a main gate and at least one sub-gate on said element formation region, said at least one sub-gate being adjacent to said main gate, said at least one sub-gate and said main gate being formed from a single unitary conductive element so that the main gate and the at least one sub-gate are in direct contact at a first portion and are separated at a second portion in a same plane;
forming at least one source/drain region of a second conductivity type between said sub gate and said element isolation region, said second conductivity type being different from said first conductivity type; and
forming at least one impurity diffusion region of said second conductivity type between said source/drain region and said main gate under said sub-gate, said impurity diffusion region having an impurity concentration lower than that of said source/drain region.