Pseudorandom number generator, semiconductor integrated circuit, pseudorandom number generator control apparatus, pseudorandom number generator control method, and computer product
In a linear feedback shift register (LFSR), a four-bit shift register mainly using F/Fs is formed and an XOR circuit that feeds back an exclusive OR of a first bit and a last bit to the first bit is also provided, thereby outputting a test pattern having a maximum cycle of 15. A phase change circuit that can perform arbitrary phase change of a test pattern based on input of a control signal having a maximum clock number 4 and an average clock number log 2 4 is also formed in the LFSR. As a result, a smaller clock count is required for the LFSR to output a test pattern that matches a test pattern automatically generated by an ATPG.
1. A pseudorandom number generator comprising:
a shift register that outputs a pseudorandom number of a plurality of bits; and
a phase change circuit that changes, based on input of a control signal, a phase for the pseudorandom number to be output by the shift register, wherein
the phase change circuit changes the phase by generating seed values to be provided to the shift register after a plurality of clocks subsequent to an output of the pseudorandom number, and inputting the seed values to the shift register.
2. The pseudorandom number generator according to claim 1 , wherein the phase change circuit performs 2 i -1 phase changes based on input of the control signal having a clock count i, where i (i=1 to n) is a bit count of the shift register.
3. The pseudorandom number generator according to claim 1 , wherein the phase change circuit changes the phase by 2 n at each clock, where n is a positive integer.
4. A semiconductor integrated circuit comprising:
a pseudorandom number generator that generates a test pattern, and includes:
a shift register that outputs a pseudorandom number of a plurality of bits, and
a phase change circuit that changes, based on input of a control signal, a phase for the
test pattern to be output by the shift register; and
a circuit-under-test that receives the test pattern output by the pseudorandom number generator, wherein
the phase change circuit changes the phase by generating seed values to be provided to the shift register after a plurality of clocks subsequent to an output of the pseudorandom number, and inputting the seed values to the shift register.
5. The semiconductor integrated circuit according to claim 4 , further comprising:
a test pattern corrector that corrects, based on input of an external control signal, the test pattern output from the pseudorandom number generator, wherein
the circuit-under-test receives the test pattern corrected by the test pattern corrector.
6. A semiconductor integrated circuit comprising:
a pseudorandom number generator that generates an indeterminate mask pattern, and includes:
a shift register that outputs a pseudorandom number of a plurality of bits, and
a phase change circuit that changes, based on input of a control signal, a phase for the indeterminate mask pattern to be output by the shift register;
a circuit-under-test; and
an indeterminate mask unit that, using the indeterminate mask pattern output from the pseudorandom number generator, masks an indeterminate value in an output pattern output from the circuit-under-test, wherein
the phase change circuit changes the phase by generating seed values to be provided to the shift register after a plurality of clocks subsequent to an output of the pseudorandom number, and inputting the seed values to the shift register.
7. The semiconductor integrated circuit according to claim 6 , wherein the indeterminate mask unit
includes an indeterminate mask pattern corrector that corrects, based on input of an external control signal, the indeterminate mask pattern output by the pseudorandom number generator, and
masks, using the indeterminate mask pattern corrected by the test pattern corrector, the indeterminate value in the output pattern output from the circuit-under-test.
8. A pseudorandom number generator control method for a pseudorandom number generator that generates a test pattern and includes a shift register that outputs a pseudorandom number of a plurality of bits and a phase change circuit that changes, based on input of a control signal, a phase for the test pattern to be output by the shift register, the pseudorandom number generator control method comprising:
acquiring a test pattern generated before phase change and an automatic test pattern generator (ATPG) pattern output from an ATPG;
extracting the ATPG pattern, acquired at the acquiring, in units of blocks;
retrieving, from the test pattern acquired at the acquiring and with respect to each block extracted at the extracting, a plurality of signals that match a plurality of signals included in a block extracted at the extracting;
determining, based on the signals retrieved at the retrieving, the control signal to be output to the pseudorandom number generator; and
outputting the control signal to the pseudorandom number generator, wherein
the control signal causes the phase change circuit to change the phase by generating seed values to be provided to the shift register after a plurality of clocks subsequent to an output of the pseudorandom number, and inputting the seed values to the shift register.
9. A pseudorandom number generator control method for a pseudorandom number generator that generates an indeterminate mask pattern and includes a shift register that outputs a pseudorandom number of a plurality of bits and a phase change circuit that changes, based on input of a control signal, a phase for the indeterminate mask pattern to be output by the shift register, the pseudorandom number generator control method comprising:
acquiring an indeterminate mask pattern generated before phase change and an output test pattern output from a circuit-under-test;
extracting the output test pattern, acquired at the acquiring, in units of blocks;
retrieving, from the indeterminate mask pattern acquired at the acquiring and with respect to each block extracted at the extracting, a plurality of signals that match a plurality of signals included in a block extracted at the extracting;
determining, based on the signals retrieved at the retrieving, the control signal to be output to the pseudorandom number generator; and
outputting the control signal to the pseudorandom number generator, wherein
the control signal causes the phase change circuit to change the phase by generating seed values to be provided to the shift register after a plurality of clocks subsequent to an output of the pseudorandom number, and inputting the seed values to the shift register.
10. The pseudorandom number generator control method according to claim 9 , wherein
the extracting the output test pattern acquired at the acquiring includes extracting the blocks such that a bit count of definitive values included in a block does not exceed a bit count of the shift register.
11. A non-transitory computer-readable recording medium storing therein a pseudorandom number generator control computer-program for a pseudorandom number generator that generates a test pattern and includes a shift register that outputs a pseudorandom number of a plurality of bits and a phase change circuit that changes, based on input of a control signal, a phase for the test pattern to be output by the shift register, wherein the pseudorandom number generator control computer-program causes a computer to execute:
acquiring a test pattern generated before phase change and an automatic test pattern generator (ATPG) pattern output from an ATPG;
extracting the ATPG pattern, acquired at the acquiring, in units of blocks;
retrieving, from the test pattern acquired at the acquiring and with respect to each block extracted at the extracting, a plurality of signals that match a plurality of signals included in a block extracted at the extracting;
determining, based on the signals retrieved at the retrieving, the control signal to be output to the pseudorandom number generator; and
outputting the control signal to the pseudorandom number generator, and wherein
the control signal causes the phase change circuit to change the phase by generating seed values to be provided to the shift register after a plurality of clocks subsequent to an output of the pseudorandom number, and inputting the seed values to the shift register.
12. A non-transitory computer-readable recording medium storing therein a pseudorandom number generator control computer-program for a pseudorandom number generator that generates an indeterminate mask pattern and includes a shift register that outputs a pseudorandom number of a plurality of bits and a phase change circuit that changes, based on input of a control signal, a phase for the indeterminate mask pattern to be output by the shift register, wherein the pseudorandom number generator control computer-program causes a computer to execute:
acquiring an indeterminate mask pattern generated before phase change and an output test pattern output from a circuit-under-test;
extracting the output test pattern, acquired at the acquiring, in units of blocks;
retrieving, from the indeterminate mask pattern acquired at the acquiring and with respect to each block extracted at the extracting, a plurality of signals that match a plurality of signals included in a block extracted at the extracting;
determining, based on the signals retrieved at the retrieving, the control signal to be output to the pseudorandom number generator; and
outputting the control signal to the pseudorandom number generator, and wherein
the control signal causing the phase change circuit to change the phase by generating seed values to be provided to the shift register after a plurality of clocks subsequent to an output of the pseudorandom number, and inputting the seed values to the shift register.
13. The computer-readable recording medium according to claim 12 , wherein
the extracting the output test pattern acquired at the acquiring includes extracting the blocks such that a bit count of definitive values included in a block does not exceed a bit count of the shift register.
14. A pseudorandom number generator control apparatus for a pseudorandom number generator that generates a test pattern and includes a shift register that outputs a pseudorandom number of a plurality of bits and a phase change circuit that changes, based on input of a control signal, a phase for the test pattern to be output by the shift register, the pseudorandom number generator control apparatus comprising:
an acquiring unit that acquires a test pattern generated before phase change and an automatic test pattern generator (ATPG) pattern output from an ATPG;
an extracting unit that extracts the ATPG pattern, acquired by the acquiring unit, in units of blocks;
a retrieving unit that retrieves, from the test pattern acquired by the acquiring unit and with respect to each block extracted by the extracting unit, a plurality of signals that match a plurality of signals included in a block extracted by the extracting unit;
a determining unit that determines, based on the signals retrieved by the retrieving unit, the control signal to be output to the pseudorandom number generator; and
an output unit that outputs the control signal to the pseudorandom number generator, wherein
the control signal causes the phase change circuit to change the phase by generating seed values to be provided to the shift register after a plurality of clocks subsequent to an output of the pseudorandom number, and inputting the seed values to the shift register.
15. A pseudorandom number generator control apparatus for a pseudorandom number generator that generates an indeterminate mask pattern and includes a shift register that outputs a pseudorandom number of a plurality of bits and a phase change circuit that changes, based on input of a control signal, a phase for the indeterminate mask pattern to be output by the shift register, the pseudorandom number generator control apparatus comprising:
an acquiring unit that acquires an indeterminate mask pattern generated before phase change and an output test pattern output from a circuit-under-test;
an extracting unit that extracts the output test pattern, acquired by the acquiring unit, in units of blocks;
a retrieving unit that retrieves, from the indeterminate mask pattern acquired by the acquiring unit and with respect to each block extracted at by the extracting unit, a plurality of signals that match a plurality of signals included in a block extracted by the extracting unit;
a determining unit that determines, based on the signals retrieved by the retrieving unit, the control signal to be output to the pseudorandom number generator; and
an output unit that outputs the control signal to the pseudorandom number generator, wherein
the control signal causes the phase change circuit to change the phase by generating seed values to be provided to the shift register after a plurality of clocks subsequent to an output of the pseudorandom number, and inputting the seed values to the shift register.
16. The pseudorandom number generator control apparatus according to claim 15 , wherein
the extracting unit extracts the blocks such that a bit count of definitive values included in a block does not exceed a bit count of the shift register.